SI5315 Просмотр технического описания (PDF) - Silicon Laboratories
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SI5315 Datasheet PDF : 54 Pages
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Si5315
SYNCHRONOUS ETHERNET/TELECOM JITTER ATTENUATING
CLOCK MULTIPLIER
Features
Provides jitter attenuation and frequency Selectable loop bandwidth for jitter
translation between SONET/PDH and
attenuation: 60 to 8.4 kHz
Ethernet
Automatic/Manual hitless switching
Supports ITU-T G.8262 Synchronous
and holdover during loss of inputs
Ethernet equipment slave clock (EEC
clock
option 1 and 2) requirements with
Programmable output clock signal
optional Stratum 3 compliant timing card format: LVPECL, LVDS, CML or
clock source
CMOS
Two clock inputs/two clock outputs
40 MHz crystal or XO reference
Input frequency range: 8 kHz–644 MHz Single supply: 1.8, 2.5, or 3.3 V
Output frequency range: 8 kHz–644 MHz On-chip voltage regulator with high
Ultra low jitter:
PSRR
0.23 ps RMS (1.875–20 MHz)
Loss of lock and loss of signal alarms
0.47 ps RMS (12 kHz–20 MHz)
Small size: 6 x 6 mm, 36-QFN
Simple pin control interface
Wide temperature range: –40 to
+85 ºC
Applications
Synchronous Ethernet line cards
SONET OC-3/12/48 line cards
PON OLT/ONU
Carrier Ethernet switches routers
MSAN / DSLAM
T1/E1/DS3/E3 line cards
Description
The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous
Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 supports SyncE
EEC options 1 and 2 when paired with a timing card that implements the required
wander filter. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz
and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to
644.53 MHz. The input clock frequency and clock multiplication ratio are selectable
from a table of popular SyncE and T1/E1 rates. The Si5315 is based on Silicon
Laboratories' third-generation DSPLL® technology, which provides any-frequency
synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the
need for external VCXO and loop filter components. The DSPLL loop bandwidth is
user programmable, providing jitter performance optimization at the application level.
Functional Block Diagram
Si5315
Clock In 1
Clock In 2
Loss of Lock
Loss of Signal 1
Loss of Signal 2
Frequency Select[3:0]
Frequency Table Select
Loop Bandwidth Select[1:0]
XTAL/Clock
DSPLL®
Status/Control
Clock Out 1
Output Signal Format[1:0]
Clock Out 2
Clock 2 Disable/PLL Bypass
VDD (1.8, 2.5, or 3.3 V)
GND
Manual/Auto Clock Selection
Clock Switch/Clock Active Indicator
XTAL/Clock
Ordering Information:
See page 48.
Pin Assignments
36 35 34 33 32 31 30 29 28
RST 1
27 FRQSEL3
FRQTBL 2
26 FRQSEL2
LOS1 3
25 FRQSEL1
LOS2 4
VDD 5
XA 6
GND
Pad
24 FRQSEL0
23 BWSEL1
22 BWSEL0
XB 7
21 CS_CA
GND 8
20 GND
AUTOSEL 9
19 GND
10 11 12 13 14 15 16 17 18
Rev. 1.0 4/12
Copyright © 2012 by Silicon Laboratories
Si5315
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