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SI5310

PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Silicon Laboratories 

Si5310

Table 2. DC Characteristics, VDD = 2.5 V, 622 Mbps (MULTSEL = 0)

(VDD = 2.5 V ±5%, TA = –40 to 85 °C)

Parameter

Symbol Test Condition Min

Typ

Max Unit

Supply Current

MULTSEL = 0

MULTSEL = 1

IDD

—

117

127

mA

—

124

134

Power Dissipation

MULTSEL = 0

MULTSEL = 1

PD

—

293

333 mW

—

310

352

Common Mode Input Voltage

(CLKIN, REFCLK)

VICM

See Figure 1

— .80 x VDD —

V

Input Voltage Range*

VIS

See Figure 1 200

—

750

mV

(CLKIN+, CLKIN–, REFCLK+, REFCLK–)

Differential Input Voltage Swing*

(CLKIN, REFCLK)

VID

See Figure 1 200

—

1500 mVPP

Input Impedance (CLKIN, REFCLK)

Differential Output Voltage Swing

(CLKOUT)

RIN

Line-to-Line

84

100

116

Ω

VOD

100 Ω Load

780

970

1260 mVPP

Line-to-Line

Differential Output Voltage Swing

(MULTOUT)

VOD

100 Ω Load

780

970

1260 mVPP

Line-to-Line

Output Common Mode Voltage

(CLKOUT, MULTOUT)

VOCM

100 Ω Load

—

VDD –

—

V

Line-to-Line

0.23

Output Impedance (CLKOUT, MULTOUT)

ROUT Single-ended

84

100

116

Ω

Output Short to GND (CLKOUT, MULTOUT) ISC(–)

—

25

31

mA

Output Short to VDD (CLKOUT, MULTOUT) ISC(+)

–17.5 –14.5

—

mA

Input Voltage Low (LVTTL Inputs)

VIL

—

—

.8

V

Input Voltage High (LVTTL Inputs)

VIH

2.0

—

—

V

Input Low Current (LVTTL Inputs)

IIL

—

—

10

µA

Input High Current (LVTTL Inputs)

IIH

—

—

10

µA

Output Voltage Low (LVTTL Outputs)

VOL

IO = 2 mA

—

—

0.4

V

Output Voltage High (LVTTL Outputs)

VOH

IO = 2 mA

2.0

—

—

V

Input Impedance (LVTTL Inputs)

RIN

10

—

—

kΩ

PWRDN/CAL Internal Pulldown Current

IPWRDN VPWRDN ≥ 0.8 V 15

25

45

µA

*Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage

swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID

min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the

positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this

range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN–, REFCLK+, or REFCLK–) must not

exceed the specified maximum Input Voltage Range (VIS max).

6

Rev. 1.2

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