SI3200 Просмотр технического описания (PDF) - Silicon Laboratories
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SI3200 Datasheet PDF : 112 Pages
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Si3220/25 Si3200/02
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter
Symbol Test Condition Min
Max Unit
Si3220/Si3225
Supply Voltage
STIPAC, STIPDC, SRINGAC, SRINGDC Current
VDD1-
VDD4
–0.5
6.0
V
–20
+20
mA
Input Current, Digital Pins
Input Voltage, Digital Pins
Analog Ground Differential Voltage
(GND1 to ePad, GND2 to ePad or GND1 to GND2)2
Digital Ground Differential Voltage
(GND3 to GND4)2
Si3200
IIN
VIND
∆VGNDA
∆VGNDD
–10
–0.3
–50
+10
mA
VDDD+0.3 V
+50
mV
–50
+50
mV
Supply Voltage
High Battery Supply Voltage3
VDD
–0.5
6.0
V
VBATH
Continuous
–104
0.4
V
10 ms
–109
0.4
V
Low Battery Supply Voltage
TIP or RING Voltage
TIP or RING Current
Si3202
VBAT,
Continuous
VBATH
0.4
V
VBATL
VTIP,
Continuous
–104
0.4
V
VRING
Pulse < 10 us VBATH–15
0.4
V
Pulse < 4 us VBATH–35 0.4
V
ITIP, IRING
–100
+100 mA
Supply Voltage
VDD
–0.5
6.0
V
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded, and exposure to absolute
maximum rating conditions for extended periods may affect device reliability. Functional operation should be restricted
to the conditions as specified in the operational sections of this data sheet.
2. The PCB pad placed under the device package must be connected with multiple vias to the PCB ground layer and to
the GND1-GND4 pins via short traces. The TQFP-64 e-Pad must be properly soldered to the PCB pad during PCB
assembly. This type of low-impedance grounding arrangement is necessary to ensure that maximum differentials are
not exceeded under any operating condition in addition to providing thermal dissipation.
3. On Si3200 revision E, the dv/dt of the voltage applied to the VBAT, VBATH, and VBATL pins must be limited to 10 V/µs.
4. Operation of the Si3220/Si3225 above 125 °C junction temperature may degrade device reliability. The Si3200/Si3202
should be operated at a junction temperature below 140 °C for optimal reliability.
5. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of equal size and that multiple vias are added to enable heat transfer between the top-side copper
surface and a large internal copper ground plane. Refer to “AN55: Dual ProSLIC® User Guide” or to the Si3220/3225
evaluation board data sheet for specific layout examples.
4
Rev. 1.3
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