SI3010 Просмотр технического описания (PDF) - Silicon Laboratories

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SI3010

GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT

Silicon Laboratories 

Si3056

Si3018/19/10

Table 4. AC Characteristics (Continued)

(VD = 3.0 to 3.6 V, TA = 0 to 70 °C; see Figure 17 on page 18)

Parameter

Symbol

Test Condition

Min Typ Max Unit

Receive Total Harmonic

Distortion8,9

Receive Total Harmonic

Distortion8,9

Dynamic Range (caller ID

mode)10,7

Caller ID Full Scale Level10

AOUT Low Level Current

THD ILIM = 0, DCV = 00, DCR = 0, —

–78

—

dB

IL = 20 mA, MINI = 11

THD ILIM = 1, DCV = 11, DCR = 0, —

–78

—

dB

IL = 50 mA, MINI = 00

DRCID

VIN = 1 kHz, –13 dBFS

—

50

—

dB

VCID

—

6

— VPEAK

—

—

10 mA

AOUT High Level Current

—

—

10 mA

Notes:

1. See Figure 26 on page 37.

2. Measured at TIP and RING with 600 Ω termination at 1 kHz, as shown in Figure 1.

3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 Ω ac termination, while

the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all

reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be

achieved with a 600 Ω ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference

impedances.

4. Receive full scale level produces –0.9 dBFS at SDO.

5. DR = 20 x log (RMS VFS/RMS VIN).+ 20 x log (RMS VIN/RMS noise). The RMS noise measurement excludes

harmonics. VFS is the 0 dBm full-scale level.

6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.

7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.

8. THD = 20 x log (RMS distortion/RMS signal). VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.

9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.

10. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log(RMS VIN/RMS noise). VCID is the 6 V full-scale level for the typical

application circuit in Figure 17. With the enhanced CID circuit, the VCID full-scale level is 1.5 V peak, and DRCID

increases to 62 dB.

11. Available on the Si3019 line-side device only.

Rev. 1.05

9

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