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SI3010

GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT

Silicon Laboratories 

Si3056

Si3018/19/10

Table 3. DC Characteristics, VD = 3.3 V

(VD = 3.0 to 3.6 V, TA = 0 to 70 °C)

Parameter

Symbol

Test Condition

Min

Typ

Max

High Level Input Voltage

VIH

2.4

—

—

Low Level Input Voltage

VIL

—

—

0.8

High Level Output Voltage

VOH

IO = –2 mA

2.4

—

—

Low Level Output Voltage

VOL

IO = 2 mA

—

—

0.35

Input Leakage Current

IL

–10

—

10

Power Supply Current, Digital1

ID

VD pin

—

15

—

Total Supply Current, Sleep Mode1

ID

PDN = 1, PDL = 0

—

9

—

Total Supply Current, Deep Sleep1,2

ID

PDN = 1, PDL = 1

—

1

—

Notes:

1. All inputs at 0.4 or VD – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded

(Static IOUT = 0 mA).

2. RGDT is not functional in this state.

Unit

V

V

V

V

µA

mA

mA

mA

Rev. 1.05

7

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