SA8807A
SERIAL INTERFACE TIMING
Ref
No Characteristic
1 Chip Enable set-up time
2 Chip Enable clock hold time
3 Clock width high
4 Clock width low
5 Data In to clock set-up time
6 Clock to Data propagation delay
7 Chip Disable to output high Z
8 Data In after clock hold time
Limits (All Types)
VDD = 3.3V
VDD = 5V
Min Max Min Max
Unit
200
100
ns
250
125
ns
400
200
ns
400
200
ns
200
100
ns
200
100 ns
200
100 ns
200
100
ns
6
5. 00
7
5. 00
MIS0
SCK
CE
DR-00846
4/14
sames