SH7055S Просмотр технического описания (PDF) - Renesas Electronics

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SH7055S

32-bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series(Hardware Manual)

Renesas Electronics 

Item

11.1.1 Features

Table 11.1 ATU-II functions

Page Revisions (See Manual for Details)

195, Table amended

196

Channel 1

(φ–φ/32) × (1/2n)

(n = 0–5)

TCLKA, TCLKB,

AGCK, AGCKM

Channel 2

(φ–φ/32) × (1/2n)

(n = 0–5)

TCLKA, TCLKB,

AGCK, AGCKM

Channels 3–5

(φ–φ/32) × (1/2n)

(n = 0–5)

TCLKA, TCLKB,

AGCK, AGCKM

GR10G

OCR10AH,

OCR10AL,

OCR10B,

NCR10,

TCCLR10

11.1.3 Register Configuration

Table 11.3 ATU-II Registers

201 Table amended

TSTR1 R/W H'00

TSTR2 R/W H'00

TSTR3 R/W H'00

PSCR1 R/W H'00

PSCR2 R/W H'00

PSCR3 R/W H'00

PSCR4 R/W H'00

11.2.2 Prescaler

Registers(PSCR)

11.2.4 Timer I/O Control

Registers(TIOR)

Timer I/O Control Registers 3A,

3B, 4A, 4B, 5A, 5B(TIOR3A,

TIOR3B, TIOR4A, TIOR4B,

TIOR5A, TIOR5B)

227 Bit Table amended

Bit: 7

6

5

4

3

2

1

0

—

—

— PSCxE PSCxD PSCxC PSCxB PSCxA

Initial value: 0

0

0

0

0

0

0

0

R/W: R

R

R

R/W R/W R/W R/W R/W

x = 1 to 4

246, Table amended

247 Bits 6 to 4

1

0

0

GR is an input Input capture disabled (In channel 3

capture register only, GR cannot be written to)

1

(input capture by Input capture in GR on rising edge at

channel 3 and 9 TIOxx pin (GR cannot be written to)

compare-match

1

0

enabled)

Input capture in GR on falling edge at

TIOxx pin (GR cannot be written to)

Bits 2 to 0

1

0

0

1

1

0

GR is an input

capture register

(input capture by

channel 3 and 9

compare-match

enabled)

Input capture disabled (In channel 3

only, GR cannot be written to)

Input capture in GR on rising edge at

TIOxx pin (GR connot be written to)

Input capture in GR on falling edge at

TIOxx pin (GR connot be written to)

Rev.2.0, 07/03, page x of xxxviii

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