R5F7142 Просмотр технического описания (PDF) - Renesas Electronics

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R5F7142

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

8.2.9 DTC Vector Base Register (DTCVBR) ............................................................ 168

8.2.10 Bus Function Extending Register (BSCEHR) .................................................. 168

8.3 Activation Sources............................................................................................................ 169

8.4 Location of Transfer Information and DTC Vector Table ................................................ 169

8.5 Operation .......................................................................................................................... 174

8.5.1 Transfer Information Read Skip Function ........................................................ 179

8.5.2 Transfer Information Write-back Skip Function............................................... 180

8.5.3 Normal Transfer Mode ..................................................................................... 180

8.5.4 Repeat Transfer Mode....................................................................................... 181

8.5.5 Block Transfer Mode ........................................................................................ 183

8.5.6 Chain Transfer .................................................................................................. 184

8.5.7 Operation Timing.............................................................................................. 186

8.5.8 Number of DTC Execution Cycles ................................................................... 187

8.5.9 DTC Bus Release Timing ................................................................................. 189

8.5.10 DTC Activation Priority Order ......................................................................... 191

8.6 DTC Activation by Interrupt............................................................................................. 192

8.7 Examples of Use of the DTC ............................................................................................ 193

8.7.1 Normal Transfer Mode ..................................................................................... 193

8.7.2 Chain Transfer when Transfer Counter = 0 ...................................................... 193

8.8 Interrupt Sources............................................................................................................... 195

8.9 Usage Notes ...................................................................................................................... 196

8.9.1 Module Standby Mode Setting ......................................................................... 196

8.9.2 On-Chip RAM .................................................................................................. 196

8.9.3 DTCE Bit Setting.............................................................................................. 196

8.9.4 Chain Transfer .................................................................................................. 196

8.9.5 Transfer Information Start Address, Source Address, and

Destination Address .......................................................................................... 196

8.9.6 Access to DTC Registers through DTC ............................................................ 196

8.9.7 Notes on IRQ Interrupt as DTC Activation Source .......................................... 197

8.9.8 Note on SCI as DTC Activation Sources.......................................................... 197

8.9.9 Clearing Interrupt Source Flag.......................................................................... 197

8.9.10 Conflict between NMI Interrupt and DTC Activation ...................................... 197

8.9.11 Operation When DTC Activation Request Is Accepted.................................... 198

Section 9 Bus State Controller (BSC)................................................................199

9.1 Features............................................................................................................................. 199

9.2 Input/Output Pins.............................................................................................................. 201

9.3 Area Overview.................................................................................................................. 202

9.3.1 Area Division .................................................................................................... 202

9.3.2 Address Map ..................................................................................................... 202

Rev. 3.00 Oct. 06, 2008 Page xi of xxiv

REJ09B0230-0300

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