SH7142 Просмотр технического описания (PDF) - Renesas Electronics

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SH7142

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

Section 7 User Break Controller (UBC)............................................................121

7.1 Features............................................................................................................................. 121

7.2 Input/Output Pins.............................................................................................................. 123

7.3 Register Descriptions........................................................................................................ 124

7.3.1 Break Address Register A (BARA) .................................................................. 125

7.3.2 Break Address Mask Register A (BAMRA)..................................................... 125

7.3.3 Break Bus Cycle Register A (BBRA)............................................................... 126

7.3.4 Break Data Register A (BDRA) ....................................................................... 128

7.3.5 Break Data Mask Register A (BDMRA) .......................................................... 129

7.3.6 Break Address Register B (BARB) .................................................................. 130

7.3.7 Break Address Mask Register B (BAMRB) ..................................................... 131

7.3.8 Break Data Register B (BDRB) ........................................................................ 132

7.3.9 Break Data Mask Register B (BDMRB)........................................................... 133

7.3.10 Break Bus Cycle Register B (BBRB) ............................................................... 134

7.3.11 Break Control Register (BRCR) ....................................................................... 136

7.3.12 Execution Times Break Register (BETR)......................................................... 141

7.3.13 Branch Source Register (BRSR)....................................................................... 142

7.3.14 Branch Destination Register (BRDR)............................................................... 143

7.4 Operation .......................................................................................................................... 144

7.4.1 Flow of the User Break Operation .................................................................... 144

7.4.2 User Break on Instruction Fetch Cycle ............................................................. 145

7.4.3 Break on Data Access Cycle............................................................................. 146

7.4.4 Sequential Break ............................................................................................... 147

7.4.5 Value of Saved Program Counter ..................................................................... 147

7.4.6 PC Trace ........................................................................................................... 148

7.4.7 Usage Examples................................................................................................ 149

7.5 Usage Notes ...................................................................................................................... 154

Section 8 Data Transfer Controller (DTC)........................................................157

8.1 Features............................................................................................................................. 157

8.2 Register Descriptions........................................................................................................ 159

8.2.1 DTC Mode Register A (MRA) ......................................................................... 160

8.2.2 DTC Mode Register B (MRB).......................................................................... 161

8.2.3 DTC Source Address Register (SAR)............................................................... 163

8.2.4 DTC Destination Address Register (DAR)....................................................... 163

8.2.5 DTC Transfer Count Register A (CRA) ........................................................... 164

8.2.6 DTC Transfer Count Register B (CRB)............................................................ 165

8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ................................... 166

8.2.8 DTC Control Register (DTCCR) ...................................................................... 167

Rev. 3.00 Oct. 06, 2008 Page x of xxiv

REJ09B0230-0300

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