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SH7144 Просмотр технического описания (PDF) - Renesas Electronics

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SH7144 Datasheet PDF : 930 Pages
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Contents
Section 1 Overview........................................................................................... 1
1.1 Features .............................................................................................................................2
1.2 Internal Block Diagram.....................................................................................................4
1.3 Pin Arrangement ...............................................................................................................6
1.4 Pin Functions ....................................................................................................................8
Section 2 CPU................................................................................................... 15
2.1 Features .............................................................................................................................15
2.2 Register Configuration ......................................................................................................15
2.2.1 General Registers (Rn).........................................................................................15
2.2.2 Control Registers .................................................................................................17
2.2.3 System Registers..................................................................................................18
2.2.4 Initial Values of Registers....................................................................................18
2.3 Data Formats .....................................................................................................................19
2.3.1 Data Format in Registers......................................................................................19
2.3.2 Data Formats in Memory .....................................................................................19
2.3.3 Immediate Data Format .......................................................................................20
2.4 Instruction Features...........................................................................................................21
2.4.1 RISC-Type Instruction Set...................................................................................21
2.4.2 Addressing Modes ...............................................................................................25
2.4.3 Instruction Format................................................................................................29
2.5 Instruction Set ...................................................................................................................32
2.5.1 Instruction Set by Classification ..........................................................................32
2.6 Processing States...............................................................................................................45
2.6.1 State Transitions...................................................................................................45
Section 3 MCU Operating Modes..................................................................... 47
3.1 Selection of Operating Modes...........................................................................................47
3.2 Input/Output Pins ..............................................................................................................49
3.3 Operating Modes...............................................................................................................50
3.3.1 Mode 0 (MCU Extension Mode 0) ......................................................................50
3.3.2 Mode 1 (MCU Extension Mode 1) ......................................................................50
3.3.3 Mode 2 (MCU Extension Mode 2) ......................................................................50
3.3.4 Mode 3 (Single Chip Mode) ................................................................................50
3.3.5 Clock Mode..........................................................................................................50
3.4 Address Map .....................................................................................................................51
3.5 Initial State in This LSI .....................................................................................................52
Rev.4.00 Mar. 27, 2008, Page ix of xliv
REJ09B0108-0400

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