SH7144 Просмотр технического описания (PDF) - Renesas Electronics

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SH7144

32-Bit RISC Microcomputer SuperH™ RISC engine

Renesas Electronics 

3.6 Note on Changing Operating Mode .................................................................................. 52

Section 4 Clock Pulse Generator .......................................................................53

4.1 Oscillator........................................................................................................................... 55

4.1.1 Connecting Crystal Resonator ............................................................................. 55

4.1.2 External Clock Input Method............................................................................... 56

4.2 Function for Detecting Oscillator Halt.............................................................................. 57

4.3 Usage Notes ...................................................................................................................... 58

4.3.1 Note on Crystal Resonator ................................................................................... 58

4.3.2 Notes on Board Design ........................................................................................ 58

Section 5 Exception Processing.........................................................................61

5.1 Overview........................................................................................................................... 61

5.1.1 Types of Exception Processing and Priority ........................................................ 61

5.1.2 Exception Processing Operations......................................................................... 62

5.1.3 Exception Processing Vector Table ..................................................................... 63

5.2 Resets ................................................................................................................................ 65

5.2.1 Types of Reset ..................................................................................................... 65

5.2.2 Power-On Reset ................................................................................................... 65

5.2.3 Manual Reset ....................................................................................................... 66

5.3 Address Errors .................................................................................................................. 67

5.3.1 Cause of Address Error Exception....................................................................... 67

5.3.2 Address Error Exception Processing.................................................................... 68

5.4 Interrupts........................................................................................................................... 69

5.4.1 Interrupt Sources.................................................................................................. 69

5.4.2 Interrupt Priority Level ........................................................................................ 70

5.4.3 Interrupt Exception Processing ............................................................................ 70

5.5 Exceptions Triggered by Instructions ............................................................................... 71

5.5.1 Types of Exceptions Triggered by Instructions ................................................... 71

5.5.2 Trap Instructions .................................................................................................. 71

5.5.3 Illegal Slot Instructions ........................................................................................ 72

5.5.4 General Illegal Instructions.................................................................................. 72

5.6 Cases when Exception Sources Are not Accepted............................................................ 73

5.6.1 Immediately after Delayed Branch Instruction .................................................... 73

5.6.2 Immediately after Interrupt-Disabled Instruction ................................................ 73

5.7 Stack Status after Exception Processing Ends .................................................................. 74

5.8 Usage Notes ...................................................................................................................... 75

5.8.1 Value of Stack Pointer (SP) ................................................................................. 75

5.8.2 Value of Vector Base Register (VBR) ................................................................. 75

5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 75

Rev.4.00 Mar. 27, 2008 Page x of xliv

REJ09B0108-0400

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