MU9C1480A Просмотр технического описания (PDF) - Music Semiconductors
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MU9C1480A Datasheet PDF : 28 Pages
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MU9C1480A/L Draft
values by using an RSC instruction. After the
LANCAM is reset, both Source and Destination counters
are set to count from Segment 0 to Segment 3 with an initial
value of 0.
Page Address Register (PA)
The Page Address register is loaded using a TCO PA
instruction followed by a Command Write cycle of a user
selected 16-bit value (not FFFFH). The entry in the PA
register is used to give a unique address to the different
devices in a daisy chain. In a daisy chain, the PA value of
each device is loaded using the SFF instruction to advance
to the next device, shown in the “Setting Page Address
Register Values” section on page 15. A software reset
(using the Control register) does not affect the Page
Address register.
Device Select Register (DS)
The Device Select register is used to select a specific (target)
device. The TCO DS instruction sets the 16-bit DS register
to the value of the following Command Write cycle. The DS
register can be read. A device is selected when its DS is
equal to its PA value. In a daisy chain, setting DS = FFFFH
will select all devices. However, in this case, the ability to
read information out of the device is restricted as shown in
Tables 5a and 5b on page 12. A software reset (using the
Control register) does not affect the Device Select register.
Address Register (AR)
The Address register points to the CAM memory location
to be operated upon when M@[AR] or M@aaaH is part of
the instruction. It can be loaded directly by using a TCO
AR instruction or indirectly by using an instruction requiring
an absolute address, such as MOV aaaH,CR,V. After being
loaded, the Address register value will then be used for the
next memory access referencing the Address register. A
reset sets the Address register to zero.
Control Register bits CT3 and CT2 set the Address register
to automatically increment or decrement (or not change)
during sequences of Command or Data cycles. The Address
register will change after executing an instruction that
includes M@[AR] or M@aaaH, or after a data access to
the end limit segment (as set in the Segment Control
register) when the persistent source or destination is
M@[AR] or M@aaaH.
Either the Foreground or Background Address register will
be active, depending on which register set has been
selected, and only the active Address register will be written
to or read from.
Next Free Address Register (NF)
The LANCAM automatically stores the address of the first
empty memory location in the Next Free Address register,
which is then used as a memory address pointer for M@NF
operations. The Next Free Address register, shown in Table
10 on page 22, can be read using a TCO NF instruction. By
taking /EC LOW during the TCO NF instruction cycle, only
the device with /FI LOW and /FF HIGH will output the
contents of its Next Free Address register, which gives the
Next Free address in a system of daisy-chained devices.
The Next Free address may be read from a specific device
in the chain by setting the Device Select register to the
value of the desired device’s Page address and leaving
/EC HIGH.
The Full Flag daisy chain causes only the device whose /FI
input is LOW and /FF output HIGH to respond to an
instruction using the Next Free address. After a reset, the
Next Free Address register is set to zero.
Status Register
The 32-bit Status register, shown in Table 11 on page 22, is
the default source for Command Read cycles. Bit 31 is the
internal Full flag, which will go LOW if the particular device
has no empty memory locations. Bit 30 is the internal
Multiple Match flag, which will go LOW if a Multiple match
was detected. Bit 29 and Bit 28 are the Skip and Empty
Validity bits, which reflect the validity of the last memory
location read. After a reset, the Skip and Empty bits will
read 11 until a read or move from memory has occurred.
The rest of the Status register down to bit 1 contains the
Page address of the device and the address of the Highest-
Priority match. After a reset or a no-match condition, the
match address bits will be all 1s. Bit 0 is the internal Match
flag, which will go LOW if a match was found in this
particular device.
Comparand Register (CR)
The 64-bit Comparand register is the default destination
for data writes and reads, using the Segment Control register
to select which 16-bit segment of the Comparand register is
to be loaded or read out. The persistent source and
destination for data writes and reads can be changed to the
mask registers or memory by SPS and SPD instructions.
During an automatic or forced compare, the Comparand
register is simultaneously compared against the CAM
portion of all memory locations with the correct validity
condition. Automatic compares always compare against
valid memory locations, while forced compares, using CMP
instructions, can compare against memory locations tagged
with any specific validity condition.
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Rev. 3.0 Draft
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