SC4809A Просмотр технического описания (PDF) - Semtech Corporation
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SC4809A Datasheet PDF : 16 Pages
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SC4809A/B/C
POWER MANAGEMENT
Application Information (Cont.)
Input and Output Capacitors
Slope Compensation
The input capacitors are chosen based upon their ripple
current rating and their rated voltage. The actual capacitor
value is not that critical as long as the minimum
capacitance gives an acceptable ripple voltage
determined by the following equation:
CMIN
=
IRMS
8 • fSW • ∆V
Sensing peak inductor current instead of average
inductor current results in a loop response that is Less
than ideal. Adding slope compensation to the current
signal cancels this error by maintaining a constant average
current independent of duty cycle. Slope compensation
is required for open loop stability in a current mode system
with 50% or greater duty cycles, but will benefit any
current mode application at the cost of a few small parts.
The output capacitors are also chosen based upon their
low equivalent series resistance (ESR), ripple current and
voltage ratings. The ripple current that the output
capacitor experiences is a result of supplying the load
current during the FET conduction time and its charging
current during the FET off-time.
Voltage Feedback
The FB pin of the SC4809 sums the voltage feedback
signal to the current sense signal and any added slope
compensation. The voltage feedback signal is from an
optocoupler, which is driven from an error amplifier on
the secondary side of the converter. The signal from the
optocoupler is designed to trip the FB threshold of the
SC4809 internal comparator when the output voltage
exceeds its specified limit.
Current Limit
Selection of the current sense resistor is accomplished
by dividing the FB threshold value by the peak primary
current at the desired current limit point. This ground-
referenced RSENSE must be a low inductance type and have
a rated power level to meet the (IRMS)2• RSENSE
requirement.
Current spikes caused by the leakage inductance of the
flyback transformer and the reverse recovery of the diode
could trip the current sense latch and prematurely shut
off the output. This unwanted spike can be suppressed
by adding a small RC filter for effective leading edge
blanking.
Loop Compensation
The continuous current mode flyback will contain a right-
half-plane (RHP) zero in its transfer function. Any increase
in load current will require the primary peak inductor
current to increase. The duty cycle must increase to
accomplish this. In a flyback converter, the inductor
current flows to the output only when the FET is off and
the diode is conducting. Increasing the duty cycle
increases the FET condition time but decreases the diode
conduction time. The result of this is the average diode
current, the current that supplies the load, actually
decreases. This is a temporary situation; as the inductor
current rises, the diode current eventually reaches its
proper value. The condition where the average diode
current must actually decrease before it can increase is
referred to as a right-half-plane zero. To complicate
matters, this zero contributes a phase lag, not a phase
lead as a normal zero would. This zero moves in frequency
as a function of load and input voltage, making it
impossible to cancel out by the insertion of a pole.
fRHPZERO
=
2 • π • ROUT
N • VIN2
• LP • (VIN
+ N • VOUT )
The easiest way to deal with a right-half-plane zero is to
roll off the loop gain at a relatively low frequency using
simple dominant pole compensation. Unfortunately, the
result of this is poor dynamic response.
The primary goal of the compensation network is to
provide good line and load regulation and dynamic
response. These objectives are best met by providing
high gain at low frequencies for good DC regulation and
high bandwidth for good transient response. Optimum
closed loop performance can only be achieved by first
2005 Semtech Corp.
11
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