SC480EVB Просмотр технического описания (PDF) - Semtech Corporation
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SC480EVB Datasheet PDF : 25 Pages
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SC480
PPOOWWEERR MMAANNAAGGEEMMEENNTT
Pin Description (Cont.)
16
17,18
19
20
21
22
23
24
ILIM
PGND1
DL
LX
DH
BST
VTTIN
VTT
Current limit input pin. Connect to drain of low-side MOSFET for RDS(on) sensing or the source
for resistor sensing through a threshold sensing resistor.
Power ground for VDDQ switching circuits. Connect to thermal pad and ground plane.
Gate drive output for the low side MOSFET switch.
Phase node - the junction between the top and bottom FETs and the output inductor.
Gate drive output for the high side MOSFET switch.
Boost capacitor connection for the high side gate drive.
Input supply for the high side switch for VTT regulator. Decouple with a 1μF capacitor to
PGND2.
Output of the linear regulator. Decouple with two (minimum) 10μF ceramic capacitors to
PGND2, locating them directly across pins 24 and 1.
T THERMAL Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected
PAD
internally.
Enable Control Logic
Enable Pin Status
Output Status
EN/PSV (1)
VTTEN
VDDQ(3)
VTT(2)
REF(2)
0
0
OFF, Discharged
(2)(3)
OFF, Discharged
(2)
OFF, Discharged
(2)
0
1
OFF, Discharged
(2)(3)
OFF, Discharged
(2)
OFF, Discharged
(2)
1
0
ON
OFF, High Impedance
ON
1
1
ON
ON
ON
Notes:
1) EN/PSV = 1 = EN/PSV high or floating.
2) Typical discharge resistances: VTT = 0.25Ω. REF = 8Ω.
3) VDDQ is discharged via external series resistance which must be added to SC480 internal discharge resistance to calculate discharge times.
This is separate from any external load on VDDQ.
FB Configuration Table
The FB pin can be configured for fixed or adjustable output voltage as shown.
FB
VDDQ(V)
VREF & VTT (V)
GND
2.5
VDDQS/2
VCCA
1.8
VDDQS/2
FB Resistors
Adjustable
VDDQS/2
Note
DDR1
DDR2
1.5V < VDDQ < 3.0V
© 2006 Semtech Corp.
8
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