POWER MANAGEMENT
Pin Configuration
TOP VIEW
DRN
1
28
TG
2
27
BST
3
26
SLP
4
25
SLPV
5
24
BOOTV
6
23
PG#
7
22
HYS
8
21
VID5
9
20
VID4
10
19
VID3
11
18
VID2
12
17
VID1
13
16
VID0
14
15
V5
BG
PGND
EN
CL
CMP
CLRF
VCCA
REFIN
GND
DAC
CORE
PG_DEL
SS
(28 Pin TSSOP)
SC453
Ordering Information
Device
SC453TSTRT
Package
TSSOP-28
Temp Range(TJ)
-40°C to + 125°C
SC453EVB
EVALUATION BOARD
Notes:
1. Only available in tape and reel packaging. A reel contains
2500 devices.
2. Lead-free package compliant with J-STD-020B. Qualified
to support maximum IR reflow temperature of 260°C for 30
seconds.
3. This device is ESD sensitive. Use of standard ESD handling
precautions is required.
4. All parameters subject to change without notice.
5. Lead-free product. This product is fully WEEE and RoHS
compliant.
Pin Descriptions
Pin#
Pin Name
1
DRN
2
TG
3
BST
4
SLP
5
SLPV
6
BOOTV
7
PG#
8
HYS
9
VID5
10
VID4
Pin Function
This pin connects to the junction of the switching and synchronous MOSFETs.
Output gate drive for the switching (high-side) MOSFET.
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop
the floating bootstrap voltage for the high-side MOSFET.
Sleep logic input signal.
Connect this pin to VCCA to select "VID Sleep Mode". Otherwise, "SLPV Sleep Mode"
is selected and the voltage on this pin sets the DAC output during sleep.
The voltage on this pin sets the BOOT-Up voltage.
Start clock indicator - open drain output. Active low.
Core Comparator Hysteresis. Connect to ground thru an external resistor called RHYS.
Hysteresis current is established by an internal VREF voltage, 1.7V, divided by RHYS.
VID most significant bit main controller voltage programming DAC input.
VID input.
© 2006 Semtech Corp.
8
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