SAA5552PS/M2A Просмотр технического описания (PDF) - Philips Electronics
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SAA5552PS/M2A Datasheet PDF : 80 Pages
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Philips Semiconductors
Standard TV microcontrollers with
On-Screen Display (OSD)
Preliminary specification
SAA55xx
7 MICROCONTROLLER
The functionality of the microcontroller used on this device
is described here with reference to the industry standard
80C51 microcontroller. A full description of its functionality
can be found in “Handbook IC20, 80C51-Based 8-bit
Microcontrollers”.
7.1 Microcontroller features
• 80C51 microcontroller core standard instruction set and
timing
• 1 µs machine cycle
• Maximum 64K × 8-bit Program ROM
• Maximum of 1.2K × 8-bit Auxiliary RAM
• Interrupt Controller for individual enable/disable with two
level priority
• Two 16-bit Timer/Counter registers
• Watchdog Timer
• Auxiliary RAM page pointer
• 16-bit Data pointer
• Idle and Power-down modes
• 29 general I/O lines
• Eight 6-bit Pulse Width Modulator (PWM) outputs for
control of TV analog signals
• One 14-bit PWM for Voltage Synthesis Tuner (VST)
control
• 8-bit Analog-to-Digital Converter (ADC) with
4 multiplexed inputs
• 2 high current outputs for directly driving LEDs
• I2C-bus byte level bus interface with dual ports.
8 MEMORY ORGANIZATION
The device has the capability of a maximum of 64-kbyte
Program ROM and 1.2-kbyte Data RAM internally.
8.1 Security bits - program and verify
SAA55xx devices have a set of security bits allied with
each section of the device, i.e. Program ROM, Character
ROM and Packet 26 ROM. The security bits are used to
prevent the ROM from being overwritten once
programmed, and also the contents being verified once
programmed. The security bits are one-time
programmable and cannot be erased.
The SAA55xx memory and security bits are structured as
shown in Fig.4. The SAA55xx security bits are set as
shown in Fig.5 for production programmed devices and
are set as shown in Fig.6 for production blank devices.
8.2 RAM organisation
The internal Data RAM is organised into two areas, Data
memory and Special Function Registers (SFRs) as shown
in Fig.7.
8.3 Data memory
The Data memory is 256 × 8-bit and occupies the address
range 00H to FFH when using indirect addressing and
00H to 7FH when using direct addressing. The SFRs
occupy the address range 80H to FFH and are accessible
using direct addressing only.
The lower 128 bytes of Data memory are mapped as
shown in Fig.8.
The lowest 24 bytes are grouped into 4 banks of
8 registers, the next 16 bytes above the register banks
form a block of bit addressable memory space.
The upper 128 bytes are not allocated for any special area
or functions.
1999 Oct 27
10
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