SAA7392 Просмотр технического описания (PDF) - Philips Electronics
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SAA7392 Datasheet PDF : 76 Pages
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Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
handbook, full pagewidth
ALE
RDi
CSi
td1
RDiL
td2
th1
DA0 to DA7
address (0:7)
IN
tsu1
th2
data (0:7)
OUT
MGR794
Fig.4 Microprocessor read protocol.
Table 2 Parallel interface timing
SYMBOL
td1
td2
th1
tsu1
th2
tsu2
th3
tWRiL
th4
td3
td4
tRDiL
DESCRIPTION
Delay ALE falling to RDi/WRi falling.
Delay CSi rising to RDi/WRi falling.
CSi hold time after RDi/WRi falling.
Address setup time before ALE falling.
Address hold time after ALE falling.
Data setup time before WRi falling.
Data hold time after WRi falling.
WRi LOW time.
ALE LOW hold time after WRi LOW.
Delay data valid after RDi LOW.
Delay RDi HIGH to data out high-impedance.
RDi LOW time.
Note
1. Tclk is the system clock period.
MIN.(1)
17
17
2Tclk + 17
17
17
0
2Tclk + 17
1Tclk + 17
3Tclk + 17
−
−
3Tclk + 128
MAX.(1)
−
−
−
−
−
−
−
−
−
3Tclk + 17
17
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2000 Mar 21
9
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