SAA7392 Просмотр технического описания (PDF) - Philips Electronics

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Компоненты Описание

производитель

SAA7392

Channel encoder/decoder CDR60

Philips Electronics 

Philips Semiconductors

Channel encoder/decoder CDR60

Preliminary specification

SAA7392

7 FUNCTIONAL DESCRIPTION

7.1 Microprocessor interfaces

The SAA7392 is programmed via two independent

microprocessor interfaces:

• Serial I2C-bus

– SDA = I2C-bus data

– SCL = I2C-bus clock

– I2C-bus write address = 3EH

– I2C-bus read address = 3FH.

• Parallel 80C51 compatible

– DA(7:0) = address/data bus

– ALE = address latch enable; latches the address

information on the bus

– WRi = active LOW write signal; write to SAA7392

– RDi = active LOW read signal; read from SAA7392

– CSi = chip select signal; gates the RDi and WRi

signals.

7.1.1 SERIAL I2C-BUS INTERFACE

Data is transferred over the interface in single bytes, via

write data or read data commands.

The sequence for a write data command is as follows:

1. Send START condition

2. Send address 3EH (write)

3. Write register address byte

4. Write data byte

5. Send STOP condition.

The sequence for a read data command is as follows:

1. Send START condition

2. Send address 3EH (write)

3. Write status register address byte

4. Send STOP condition

5. Send address 3FH (read)

6. Read data byte

7. Send STOP condition.

7.1.2 PARALLEL INTERFACE

The parallel interface has a multiplexed address/data bus.

Information can be written to or read from the SAA7392

using the protocols shown in Figs 3 and 4; specific timings

are shown in Table 2. Note that only the lower six address

bits are decoded; so writing to address 40H would have

the same effect as writing to address 00H.

handbook, full pagewidth

ALE

WRi

CSi

td1

t WRiL

td2

th1

DA0 to DA7

address (0:7)

IN

tsu1

th2

data (0:7)

IN

tsu2

Fig.3 Microprocessor write protocol.

2000 Mar 21

8

MGR793

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