SAA7392 Просмотр технического описания (PDF) - Philips Electronics

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Компоненты Описание

производитель

SAA7392

Channel encoder/decoder CDR60

Philips Electronics 

Philips Semiconductors

Channel encoder/decoder CDR60

Preliminary specification

SAA7392

6.2 Pin description

Table 1 LQFP80 package; note 1

SYMBOL

WREFLO

WREFHI

WREFMID

VSSA1

VDDA1

WIN

VREF

IREF

n.c.

HREFHI

HREFLO

AGCREF

HIN

HREFMID

VDDA2

VSSA2

TEST1

TEST2

VSSD

VDDE

XTLI

XTLO

OTD

MUXSWI

W441

ATIPSYC

PANIC

PORE

CL1

VDDD

VSSD

SCL

SDA

INT

DA7

DA6

DA5

DA4

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19, 43, 62, 71

20

21

22

23

24

25

26

27

28

29

30, 49, 53, 76

31, 48, 52, 75

32

33

34

35

36

37

38

TYPE

O

O

O

supply

supply

I

O

O

−

O

O

I

I

O

supply

supply

I

I

supply

supply

I

O

I

I

O

O

I

I

O

supply

supply

I

I/O

O

I/O

I/O

I/O

I/O

DESCRIPTION

wobble ADC analog reference voltage

wobble ADC analog reference voltage

wobble ADC analog reference voltage

analog ground

3 V analog supply voltage 1; note 2

wobble analog input

analog voltage reference

analog current reference

not connected

HF ADC analog reference voltage

HF ADC analog reference voltage

AGC analog reference voltage

HF analog data input

HF ADC analog reference voltage

3 V analog supply voltage 2; note 2

analog ground

test input 1

test input 2

output driver ground

output driver 3 V supply voltage

crystal oscillator input

crystal oscillator output

off track detect input

clock multiplier enable

wobble 44.1 kHz clock output

ATIPSync output

laser low power (LLP)

power-on reset

divided clock output

core and pad ring 3 V supply voltage; note 2

core and pad ring ground

sub-CPU clock

bidirectional sub-CPU data

sub-CPU interrupt

bidirectional sub-CPU parallel data bus

bidirectional sub-CPU parallel data bus

bidirectional sub-CPU parallel data bus

bidirectional sub-CPU parallel data bus

2000 Mar 21

6

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