SAA7392 Просмотр технического описания (PDF) - Philips Electronics
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SAA7392 Datasheet PDF : 76 Pages
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Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
1 FEATURES
• Very high speed Compact Disc (CD) compatible
decoding and encoding device
• On-chip Analog-to-Digital Converter (ADC) and
Automatic Gain Control (AGC) for HF data capture
• Eight-to-Fourteen Modulation (EFM)
• Advanced motor control loop to allow CAV, CLV and
pseudo-CLV playback
• Integrated FIFO for de-coupling of mechanism speed
and application speed
• Versatile output interface allowing different I2S-bus and
Electronic Industries Association of Japan (EIAJ)
formats
• Device is fully compatible with ELM, PLUM and Sanyo
CD-ROM block decoders
• Quad-pass CIRC correction for CD mode
(C1-C2-C1-C2)
• Subcode/header processing for CD format
• Frequency multiplier allows use of a 8 MHz crystal.
2 GENERAL DESCRIPTION
CDR60 is a channel encoder/decoder for
CD/CD-R/CD-RW/CD Audio Recorder systems. It
incorporates all logic and RAM required for the complete
encoding and decoding processes.
There are two main datapaths through the CDR60 device.
The decode datapath captures the incoming EFM data
stream via the HF ADC and AGC functions.
The bit detector recovers the individual bits from the
incoming signal, correcting asymmetry, performing noise
filtering and equalisation, and recovering the channel bit
clock using a digital PLL. The demodulator converts the
EFM bits to byte-wide data symbols, before passing them
onto the decoder for subcode extraction, de-interleaving
and error correction. The decoded data is then made
available via the multi-function serial output interface.
The encode datapath takes data symbols from the block
encoder/decoder via the serial data and subcode input
functions, encoding them via the encoder block. The
encoded data stream is passed to the EFM modulator,
which generates the required EFM signal, output as a
digital bit stream. The encode process is controlled via the
Wobble processor, encode control and EFM clock
generator functions.
As well as these two data processing sections, three
further blocks support overall device operation. The
system clock generator provides all digital clocks required
by the CDR60. The motor servo allows the CDR60 to
control the spindle motor and is controlled by the
microprocessor interface. This interface can be accessed
either via a parallel (80C51) or a serial (I2C-bus) interface.
3 QUICK REFERENCE DATA
SYMBOL
VDDD
VDDA
VDDE
IDD
fxtal
Tamb
Tstg
PARAMETER
supply voltage (core and pad ring)
supply voltage (analog)
supply voltage (output drivers)
supply current
crystal frequency
operating ambient temperature
storage temperature
MIN.
3.0
3.0
3.0
−
8
0
−55
TYP.
3.3
3.3
3.3
200
8.4672
−
−
MAX.
3.6
3.6
3.6
−
33
70
+125
UNIT
V
V
V
mA
MHz
°C
°C
4 ORDERING INFORMATION
TYPE
NUMBER
SAA7392HL
NAME
LQFP80
PACKAGE
DESCRIPTION
plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm
2000 Mar 21
3
VERSION
SOT315-1
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