SAA7392 Просмотр технического описания (PDF) - Philips Electronics
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SAA7392 Datasheet PDF : 76 Pages
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Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.2.4 INTERRUPT ENABLE REGISTER (INTEN)
Table 9 Interrupt Enable Register (address 0BH) - WRITE
7
6
5
4
3
2
1
0
Sema1En Sema2En Sema3En LockInEn HeaderValen MotorOverflowEn FIFOOvEn
−
Table 10 Description of IntEn bits
BIT
SYMBOL
DESCRIPTION
7
Sema1En If Sema1En = 1, then Semaphore Register 1 interrupt is enabled.
6
Sema2En If Sema2En = 1, then Semaphore Register 2 interrupt is enabled.
5
Sema3En If Sema3En = 1, then Semaphore Register 3 interrupt is enabled.
4
LockInEn
If LockinEn = 1, then channel data PLL in lock interrupt is enabled.
3
HeaderValEn If HeaderValEn = 1, then new header/subcode available interrupt is enabled.
2 MotorOverflowEn If MotorOverflowEn = 1, then motor overflow interrupt is enabled.
1
FIFOOvEn If FIFOOvEn = 1, then FIFO overflow interrupt is enabled.
0
−
This bit is reserved.
7.2.5 STATUS REGISTER 2 (STATUS2)
Table 11 Status Register 2 (address 20H) - READ/WRITE
7
BankSwitch
6
SyncError
5
DataNotValid
4
QSync
3
ATIPSync
2
LaserOn
1
LaserOff
0
XErrorLarge
Table 12 Description of Status2 bits
BIT
SYMBOL
DESCRIPTION
7
BankSwitch When set a ‘Bank switch’ in the subcode insert block has occurred; reset when a logic 1
is written to this bit.
6
SyncError When set synchronisation with PLUM on subcode transfer has failed; reset when a
logic 1 is written to this bit.
5
DataNotValid When set an under-run on subcode transfer with PLUM has occurred; reset when a
logic 1 is written to this bit.
4
QSync
When set a Q-channel subcode sync has been written to disc; reset when a logic 1 is
written to this bit.
3
ATIPSync
When set sync has been found in the ATIP channel; reset when a logic 1 is written to
this bit.
2
LaserOn
When set a rising edge of the internal LaserOn signal has occurred; reset when a
logic 1 is written to this bit.
1
LaserOff
When set a falling edge of the internal LaserOn signal has occurred; reset when a
logic 1 is written to this bit.
0
XErrorLarge When set the offset between QSync and ATIPSync is more than 2 EFM frames different
from the programmed value.
2000 Mar 21
14
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