Philips Semiconductors
Integrated MPEG AVGD decoders
Preliminary specification
SAA7215; SAA7216; SAA7221
FEATURES
General features
• Integrated MPEG AVGD decoder: audio, video and
graphics decoding and digital video encoding
• 5 planes display chain: background colour, background
plane, MPEG display plane, graphics plane and cursor
plane
• 16-Mbit or 32-Mbit external Synchronous DRAM
(SDRAM) for MPEG audio and video decoding and
graphics data storage
• Single or double external SDRAM organized as
1 M × 16 or 2 × 1 M × 16 (two independent 16-bit data
bus) interfacing at 81 MHz. Due to efficient memory use
in MPEG decoding, more than 1 Mbit is available for
graphics in the single SDRAM configuration whereas
17 Mbits are available in the double SDRAM
configuration.
• All basic operations of the AVGD decoder are possible
in both 16- and 32-Mbit configuration; enhanced
performance is achieved by the use of 32-Mbit external
SDRAM
• Targeted to BSkyB 3.0 and Canal+ basic box and web
box specifications
• Fast 16-bit data + 22-bit address synchronous or
asynchronous interface with external controller at up to
40.5 MHz
• Dedicated input for compressed audio and video in
Packetized Elementary Stream (PES) or Elementary
Stream (ES) in byte wide or bit serial format.
Accompanying strobe signals distinguish between audio
and video data. Transport stream error correction
available.
• Audio and/or video can also be input via the CPU
interface in PES or ES in 8 or 16-bit parallel format
• Single 27 or 40.5 MHz external clock for time base
reference and internal processing. Internal system time
base at 90 kHz can be synchronized via CPU port.
All required decoding and presentation clocks are
generated internally.
• Flexible memory allocation under control of the external
CPU enables optimized partitioning of memory for
different tasks
• Optimum compatibility with T-MIPS controller family
(SAA7214, SAA7219 and successors)
• Boundary scan testing implemented
• External SDRAM self test
• Supply voltage: 3.3 V; package: SQFP208.
CPU related features
• 16-bit data, 22-bit address, Chip Select, Data Strobe
and DaTa ACKnowledge external control protocol
• Fast 16-bit data plus 22-bit address synchronous
interface with the SAA7214, SAA7219 family at up to
40.5 MHz
• Asynchronous interface possible with external
microcontroller
• Support of fast DMA transfer
• Flexible bidirectional interface to external SDRAM
• High speed/low latency interface with second graphics
SDRAM
• Byte access to the full SDRAM in the upper 16-Mbit
address range
• Independent memory mapping of SDRAM and control
registers
• Two programmable independent interrupt lines
available
• Supports Motorola 68xxx interfaces as well as LSI
L64108 interface.
MPEG-2 system features
• Parsing of MPEG-2 PES and MPEG-1 packet streams
• Double system time clock counters
• Stand-alone or supervised audio/video synchronization
• Processing of errors flagged by channel decoding
section.
MPEG-2 video features
• Decoding of MPEG-2 video up to main level, main profile
• Output picture format: CCIR-601 4 : 2 : 2 interlaced
pictures. Picture format 720 × 576 at 50 Hz or 720 × 480
at 60 Hz.
• Support of constant and variable bit rates up to
15 Mbits/s for the elementary stream
• Horizontal and vertical pan and scan allows the
extraction of a window from the coded picture
• Flexible horizontal scaling from 0.5 up to 4 allows easy
aspect ratio conversion including support for 2.21 : 1
aspect ratio movies; in case of shrinking an anti-aliasing
pre-filter is applied
2000 Jan 31
2