SAA7219HS Просмотр технического описания (PDF) - Philips Electronics
Номер в каталоге
Компоненты Описание
производитель
SAA7219HS Datasheet PDF : 20 Pages
| |||
5.2 Pin description
Table 1 SQFP208 package: 179 functional pins and 29 power supply pins
SYMBOL
PIN
I/O
BUFFER TYPE
VOLT(1)
DESCRIPTION
PIO interface (32 pins)
PIO0 to PIO7
PIO8/BOOTIS32
PIO9/BOOTIS16
PIO10 to PIO15
PIO(31:16)/D(31:16)
105 to 112
113
114
I/O bidirectional, 3 mA output drive 5 V
I/O bidirectional, 3 mA output drive 5 V
I/O bidirectional, 3 mA output drive 5 V
116 to 121
I/O bidirectional, 3 mA output drive 5 V
2, 4 to 9, 11 to 16, I/O bidirectional, 6 mA output drive 5 V
18 to 20
usable as interrupt inputs and/or I/O lines
PIO bit and PIO-strap. At power-on, it indicates the
data bus size of the booting device.
PIO bit and PIO-strap. At power-on, if BOOTIS32 is
LOW, it indicates if the system should reboot from a
16-bit or 8-bit device.
PIO bit and PIO-strap
I/O lines or upper 16-bit data bus. The data bus
width of the booting device is automatically
configured at power-on.
Extension bus (58 pins)
D15 to D0
21, 22, 24, 25,
I/O bidirectional, 8 mA output drive 3.3 V
28 to 30, 33 to 36,
38 to 41
A0 to A21
63 to 65, 67 to 71, O
73 to 77, 81 to 85,
87 to 90
8 mA output drive
3.3 V
RAS0N
49
O 8 mA output drive
3.3 V
RAS1N/DCS1N
48
O 8 mA output drive
3.3 V
LCASN
46
O 8 mA output drive
3.3 V
MLCASN
43
O 8 mA output drive
3.3 V
MUCASN
44
O 8 mA output drive
3.3 V
UCASN
42
O 8 mA output drive
3.3 V
WEN
62
O 8 mA output drive
3.3 V
DCS0N
47
O 8 mA output drive
3.3 V
CS6N to CS0N
50 to 56
O 8 mA output drive
3.3 V
OEN
58
O 8 mA output drive
3.3 V
DTACKN
59
I TTL input
5V
CS_SDN
60
O 2 mA output drive
3.3 V
lower 16-bit data bus
address bus
row access strobe for DRAM and SDRAM Bank 0
row access strobe for DRAM and SDRAM Bank 1
column access strobe lower byte
column access strobe mid lower byte
column access strobe mid upper byte
column access strobe upper byte
write enable
chip select for SDRAM Bank 0
chip select
output enable
Data termination acknowledge. Asserted LOW by
the peripheral when the data bus is valid.
selects the graphics SDRAM memory space of the
SAA7215
Share Link: 