SAA7120 Просмотр технического описания (PDF) - Philips Electronics
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SAA7120 Datasheet PDF : 32 Pages
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Philips Semiconductors
Digital Video Encoder (ConDENC)
Preliminary specification
SAA7120; SAA7121
Y and C signals are also combined to a 10-bit CVBS
signal.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitude at the input of
the DAC for CVBS is reduced by 15⁄16 with respect to
Y and C DACs to make maximum use of conversion
ranges.
Outputs of the DACs can be set together in two groups via
software control to minimum output voltage for either
purpose.
On the RCV2 port, the device can provide a horizontal
synchronization pulse with programmable start and stop
phase; this pulse can be inhibited in the vertical blanking
period to build up, for example, a composite blanking
signal.
The polarity of both RCV1 and RCV2 is selectable by
software control.
The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
Synchronization
Synchronization of the ConDENC is able to operate in two
modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and the on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.
If the horizontal phase is not to be influenced by RCV1, a
horizontal synchronization pulse needs to be supplied at
the pin RCV2. Timing and trigger behaviour can also be
influenced by RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time
base of ConDENC runs free, thus an arbitrary number of
synchronization slopes may be absent, but no additional
pulses (with the incorrect phase) must occur.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Alternatively, the device can be triggered by auxiliary
codes in a “CCIR 656” data stream at the MP port.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the device can
output:
• A Vertical Synchronisation signal (VS) with 3 or 2.5 lines
duration, or
• An ODD/EVEN signal which is LOW in odd fields, or
• A field sequence signal (FSEQ) which is HIGH in the first
of 4 or 8 fields respectively.
Teletext timing
The teletext timing is shown in Fig.7. tFD is the time needed
to interpolate input data TTX and inserting it into the
CVBS and Y output signal, such that it appears at
tTTX = 10.2 µs (PAL) or tTTX = 10.5 µs (NTSC) after the
leading edge of the horizontal synchronization pulse.
Time tPD is the pipeline delay time introduced by the
source that is gated by TTXRQ in order to deliver TTX
data. This delay is programmable by register TTXHD.
For every active HIGH-state at output pin TTXRQ, a new
teletext bit must be provided by the source.
Since the beginning of the pulses representing the TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of outgoing
horizontal synchronization pulse.
Time tTTXWin is the internally used insertion window for
TTX data; it has a constant length that allows insertion of
360 teletext bits at a text data rate of 6.9375 Mbits/s
(PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s
(World Standard TTX) or 288 teletext bits at a text data
rate of 5.7272 Mbits/s (NABTS). The insertion window is
not opened if the control bit TTXEN is logic 0.
Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.
1997 Jan 06
9
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