SAA5250 Просмотр технического описания (PDF) - Philips Electronics

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SAA5250

Interface for data acquisition and control (for multi-standard teletext systems)

Philips Electronics 

Philips Semiconductors

Interface for data acquisition and control

(for multi-standard teletext systems)

Product specification

SAA5250

Clock generation

The clock generator does the following:

• acts as a buffer for the DCK clock

• generates the character clock

As soon as a framing code has been detected, a divide by 8 counter is initialized and the character clock is started. The

clock drives the following:

• sequence controller

• parallel registers

• format counter

Processing of VAL and CBB signals

The circuit has one input (VAL IN/SYNC) and two outputs (VAL OUT and CBB). The circuit consists of:

• 7-bit counter operating at DCK frequency which produces the framing code validation pulse delay

• 7-bit comparator which compares the contents of the R5 register (bits R56 to R50) to the bit counter

• a 6-bit counter operating at DCK frequency which produces the CBB pulse width

• 6-bit comparator which compares the contents of the R7 register (bits R75 to R70) to the bit counter

• control logic required to provide the start condition for the VAL signal and the CBB pulse width (on the negative or

positive edge of the sync signal)

The CBB signal useful occurs when the associated video processor:

• has no sandcastle pulse to send back to the demodulator

• carries out the synchronization of the time base clock. In this event the CBB acts as a data slicer reset pulse

The VAL OUT is a control signal which reflects the internal framing code window.

Prefix processing (see Table 21)

Figs 4 to 9 show the acquisition flow charts for each prefix type coded in the R0 register (bits R02 to R00).

As soon as an initialization command is received by the CIDAC, a write command to the R6 register (only the address is

significant), is ready to receive data from a dedicated channel number and store the data in the FIFO memory (explained

in the following paragraphs, each paragraph being dedicated to an individual type of prefix).

DIDON long (see Fig.4)

In this mode, the continuity index, format and data bytes are written into the FIFO memory. (In fast mode, information

can be written into the FIFO memory only after a page detection.)

January 1987

15

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