SAA5250 Просмотр технического описания (PDF) - Philips Electronics

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SAA5250

Interface for data acquisition and control (for multi-standard teletext systems)

Philips Electronics 

Philips Semiconductors

Interface for data acquisition and control

(for multi-standard teletext systems)

Product specification

SAA5250

Operation

The CIDAC uses the same clock signal for data acquisition and internal processing, this allows the CIDAC to have a write

and a read cycle during each character period (see Fig.13). The first half of the character period is a write cycle and the

second half is a read cycle. Consequently, for an 8 MHz bit rate the maximum memory cycle time is 500 ns.

When the first data byte is written into the FIFO memory, thus transferred into the read register, the FIFO memory enters

the status shown in Table 12.

Table 12 FIFO status

DB2 TO DB0

DB2 = 1

memory empty

DB1 = 0

data available

DB0 = 0

memory not full

When the FIFO memory is full two events occur:

• the write address register points to the next address after the last written address

• when new data is to be written, the memory select signal output ceases

Memory interface

The memory interface contains all the buffers for the memory signals mentioned in the section ‘FIFO memory controller’.

Page detection

This part of the CIDAC contains a parallel register with logic which detects (only in fast mode) a start of a page or data

group (see section ‘R0 register’).

Hamming correction (see Tables 13 and 14)

The Hamming correction provides (see section ‘Prefix processing’):

• hexadecimal value of the Hamming code

• accept/reject code signal

• parity information

January 1987

12

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