SAA4956TJ/V1 Просмотр технического описания (PDF) - Philips Electronics

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SAA4956TJ/V1

2.9-Mbit field memory with noise reduction

Philips Electronics 

Philips Semiconductors

2.9-Mbit field memory with noise reduction

Preliminary specification

SAA4956TJ

handbook, halfpage

SCL 1

40 NREN

GND 2

39 OGND

D11(Y7) 3

38 Q11(Y7)

D10(Y6) 4

37 Q10(Y6)

D9(Y5) 5

36 Q9(Y5)

D8(Y4) 6

35 Q8(Y4)

D7(Y3) 7

34 Q7(Y3)

D6(Y2) 8

33 Q6(Y2)

D5(Y1) 9

32 Q5(Y1)

D4(Y0) 10

31 Q4(Y0)

D3(U1) 11 SAA4956TJ 30 Q3(U1)

D2(U0) 12

29 Q2(U0)

D1(V1) 13

28 Q1(V1)

D0(V0) 14

27 Q0(V0)

SWCK 15

26 SRCK

RSTW 16

25 RSTR

WE 17

24 RE

IE 18

23 OE

VDD 19

SDA 20

22 VDD(O)

21 VDD(P)

MGR688

Fig.2 Pin configuration.

the read operation frequency. In this case the random

block access modes are not supported because a second

read operation (READ2) is activated with an identical

frequency as used in the write operations. The PAN-IC

(SAA4995WP) needs approximately the same write

frequency for the noise reduction option as the read

frequency (32 MHz). To allow this configuration the

self-refresh must be switched off via the I2C-bus interface.

7.1.1 WRITE OPERATION

Write operations are controlled by the SWCK, RSTW, WE

and IE signals. A write operation starts with a reset write

address pointer (RSTW) operation, followed by a complete

cycle of the SWCK clock during which time WE and IE

must be held HIGH. Write operations between two

successive reset write operations must contain at least

40 SWCK write clock cycles while WE is HIGH. To transfer

data temporarily stored in the serial write registers to the

memory array, a reset write operation is required after the

last write operation.

7.1.1.1 Reset write: RSTW

The first positive transition of SWCK after RSTW goes

from LOW-to-HIGH resets the write address pointer to the

lowest address (−12 decimal), regardless of the state of

WE (see Figs 4 and 5). RSTW set-up (tsu(RSTW)) and hold

(th(RSTW)) times are referenced to the rising edge of SWCK

(see Fig.4). The reset write operation may also be

asynchronously related to the SWCK signal if WE is LOW.

RSTW needs to stay LOW for a single SWCK cycle before

another reset write operation can take place. If RSTW is

HIGH for 1024 SWCK write clock cycles while WE is

HIGH, the SAA4956TJ will enter a built-in test mode.

7 FUNCTIONAL DESCRIPTION

The functional description is divided into 3 main sections:

• The basic field memory function (see Section 7.1)

• The optional noise reduction function (used in case the

NREN signal is HIGH; see Section 7.2)

• The I2C-bus interface function (which controls the noise

reduction circuit; see Section 7.3).

7.1 Field memory function

The basic field memory function is fully compatible with the

SAA4955TJ if the NREN signal is LOW. In this case the

noise reduction function is bypassed via a data mux. If the

NREN signal is HIGH the basic field memory function can

only be executed with a write frequency restricted to half of

7.1.1.2 Random write block access mode

The SAA4956TJ will enter random write block access

mode if the following signal sequence is applied to control

inputs IE and WE during the first four SWCK write clock

cycles after a reset write (see Figs 6 and 7):

1. At the 1st and 2nd positive transitions of SWCK,

IE must be LOW and WE must be HIGH

2. At the 3rd and 4th positive transitions of SWCK,

IE must be HIGH and WE must be LOW

3. At the 5th positive transition of SWCK, the state of WE

determines which input pin is used for the block

address. If WE is LOW the Most Significant Bit (MSB)

of the block address must be applied to the D0 input

pin. If WE is HIGH, the MSB of the block address is

applied to pin IE.

1998 Dec 08

7

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