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S4242 Просмотр технического описания (PDF) - Summit Microelectronics

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S4242 Datasheet PDF : 16 Pages
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S4242/S42WD42/S4261/S42WD61
PIN CONFIGURATIONS
8-Pin PDIP
or 8-Pin SOIC
VLOW# 1
RESET# 2
VSENSE 3
GND 4
8 VCC
7 RESET
6 SCL
5 SDA
2025 T PCon 2.0
PB_RST#
PIN NAMES
Symbol
VLOW#
RESET#
VSENSE
GND
SDA
SCL
RESET
VCC
VCC = 3.0V or 5.0V
Pin
Description
1
Open drain output, active when
VSENSE < 1.24V
2 Active low I/O
3
2nd monitor voltage input.VLOW#
output when < 1.24V
4 Analog & digital ground
5 Serial memory I/O data line
6 Serial memory clock
7 Active high I/O
8 Supply voltage
VBAT TO
REGULATOR
VBAT
TRIP
S42xxx
VLOW#
RESET#
VSENSE
GND
VCC
RESET
SCL
SDA
I2C Peripheral
INTO (P1.5)
8051 Type
MCU
RST
SCL (P0.0)
SDA (P0.1)
RESET#
SCL
SDA
2025 T fig06 2.0
FIGURE 6. TYPICAL SYSTEM CONFIGURATION USING A PUSH BUTTON RESET AND BATTERY MONITOR CIRCUIT
SECOND CARD
VOLTAGE
3.0V ±5%
VCC = 5.0V ±10%
S42xxx
VLOW#
RESET#
VSENSE
GND
VCC
RESET
SCL
SDA
General
Purpose
MCU
SCL
SDA
I2C Peripheral
RESET#
RESET#
SCL
SDA
2025 T fig07 2.0
FIGURE 7. TYPICAL SYSTEM CONFIGURATION FOR DUAL RESET WITH VCC MONITOR AND 3.3VOLT MONITOR
2025 6.0 4/17/00
6

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