S3C72Q5 Просмотр технического описания (PDF) - Samsung

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производитель

S3C72Q5

4–BIT CMOS MICROCONTROLLER

Samsung 

Table

Number

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

3-1

3-2

3-3

3-4

4-1

4-2

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

5-18

5-19

5-20

6-1

6-2

6-3

6-4

6-5

6-6

List of Tables

Title

Page

Number

Pin Descriptions ..................................................................................................1-5

Program Memory Address Ranges........................................................................2-1

Data Memory Organization and Addressing ...........................................................2-7

Working Register Organization and Addressing......................................................2-10

BSC Register Organization...................................................................................2-16

Program Status Word Bit Descriptions ..................................................................2-17

Interrupt Status Flag Bit Settings ..........................................................................2-18

Valid Carry Flag Manipulation Instructions .............................................................2-21

RAM Addressing Not Affected by the EMB Value...................................................3-4

1-Bit Direct and Indirect RAM Addressing ..............................................................3-6

4-Bit Direct and Indirect RAM Addressing ..............................................................3-8

8-Bit Direct and Indirect RAM Addressing ..............................................................3-11

I/O Map for Memory Bank 15................................................................................4-2

I/O Map for Memory Bank 15................................................................................4-3

Valid 1-Byte Instruction Combinations for REF Look-Ups ........................................5-2

Bit Addressing Modes and Parameters..................................................................5-4

Skip Conditions for ADC and SBC Instructions .......................................................5-5

Data Type Symbols .............................................................................................5-6

Register Identifiers ...............................................................................................5-6

Instruction Operand Notation ................................................................................5-6

Opcode Definitions (Direct)...................................................................................5-7

Opcode Definitions (Indirect).................................................................................5-7

CPU Control Instructions — High-Level Summary ...................................................5-9

Program Control Instructions — High-Level Summary .............................................5-9

Data Transfer Instructions — High-Level Summary..................................................5-10

Logic Instructions — High-Level Summary .............................................................5-11

Arithmetic Instructions — High-Level Summary ......................................................5-11

Bit Manipulation Instructions — High-Level Summary..............................................5-12

CPU Control Instructions — Binary Code Summary ................................................5-14

Program Control Instructions — Binary Code Summary ..........................................5-15

Data Transfer Instructions — Binary Code Summary...............................................5-16

Logic Instructions — Binary Code Summary ..........................................................5-18

Arithmetic Instructions — Binary Code Summary ...................................................5-19

Bit Manipulation Instructions — Binary Code Summary...........................................5-20

Power Control Register (PCON) Organization.........................................................6-4

Instruction Cycle Times for CPU Clock Rates.........................................................6-5

System Clock Mode Register (SCMOD) Organization.............................................6-6

Main Oscillation Stop Mode..................................................................................6-7

Elapsed Machine Cycles During CPU Clock Switch................................................6-8

Clock Output Mode Register (CLMOD) Organization...............................................6-10

S3C72Q5/P72Q5 MICROCONTROLLER

xv

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