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S3C24A0

AN APPLICATION PROCESSOR FOR 2.5G/3G MOBILE PHONES

Samsung 

S3C24A0 RISC MICROPROCESSOR

BSW rv0.1-0417-N01

PRELIMINARY PRODUCT OVERVIEW

1 INTRODUCTION (PRELIMINARY)

1.1 ARCHITECTURAL OVERVIEW

The S3C24A0 is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low power, and

high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W

performance for the 2.5G & 3G communication services, the S3C24A0 adopts dual-32-bit bus architecture and

includes many powerful hardware accelerators for the motion video processing, serial communications, and etc.

For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated. To reduce total

system cost and enhance overall functionality, the S3C24A0 also includes following components: separate 16KB

Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (TFT), Camera

Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager (power management & etc.),

SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IIC-BUS interface, USB Host, SD Host

& Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0 can be used

as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0 has a Modem

Interface to communicate with various Modem Chips.

The S3C24A0 is developed using an ARM926EJ-S core, advanced 0.13um CMOS standard cells and memory

compliers. Its low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-sensitive

and power-sensitive applications. Also, the S3C24A0 adopts a de-facto standard bus architecture – the AMBA

(Advanced Microcontroller Bus Architecture).

One of outstanding features of the S3C24A0 is its CPU core, a 16/32-bit ARM926EJ-S RISC processor designed

by ARM, Ltd. The ARM926EJ-S is a single chip MCU and Java enabled microprocessor. The ARM926EJ-S also

implements the MMU, the AMBA BUS, and the Harvard cache architecture with separate 16KB instruction and

16KB data caches, each cache with an 8-word line length.

By providing a complete set of common system peripherals, the S3C24A0 minimizes overall system costs and

eliminates the need to configure additional components.

1.2 FEATURES

This section summarizes the features of the S3C24A0. Figure 1-1 is an overall block diagram of the S3C24A0.

1.2.1 Microprocessor and Overall Architecture

• SoC (System-on-Chip) for mobile phones and general embedded applications.

• 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.

• ARM’s Jazelle Java technology

• Enhanced ARM architecture MMU to support WinCE, Symbian and Linux

• Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main

memory bandwidth and latency on performance

1-3

Preliminary product information describes products that are in development,

for which full characterization data and associated errata are not yet available.

Specifications and information herein are subject to change without notice.

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