S3C2410A Просмотр технического описания (PDF) - Samsung

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производитель

S3C2410A

200MHz & 266MHz 32-Bit RISC Microprocessor

Samsung 

Table of Contents (Concluded)

Appendix 3- MMU (Continued)

Level Two Descriptor............................................................................................................................3-11

Translating Large Page References .......................................................................................................3-12

Translating Small Page References .......................................................................................................3-14

Translating Tiny Page References .........................................................................................................3-15

Sub-Pages..........................................................................................................................................3-17

Mmu Faults and CPU Aborts................................................................................................................3-17

Fault Address and Fault Status Registers..............................................................................................3-18

Fault Status ................................................................................................................................3-18

Domain Access Control .......................................................................................................................3-19

Fault Checking Sequence ....................................................................................................................3-21

Alignment Fault...........................................................................................................................3-22

Translation Fault..........................................................................................................................3-22

Domain Fault ..............................................................................................................................3-22

Permission Fault .........................................................................................................................3-23

External Aborts ...................................................................................................................................3-24

Interaction of the MMU and Caches.......................................................................................................3-25

Enabling the MMU.......................................................................................................................3-25

Disabling the MMU......................................................................................................................3-25

Appendix 4- Caches, Write Buffer

About the Caches and Write Buffer .......................................................................................................4-1

Instruction Cache ................................................................................................................................4-2

Instruction Cache Enable/Disable..................................................................................................4-3

Instruction Cache Operation .........................................................................................................4-3

Instruction Cache Replacement Algorithm......................................................................................4-4

Instruction Cache Lockdown.........................................................................................................4-4

Data Cache and Write Buffer ................................................................................................................4-5

Data Cache and Write Buffer Enable/Disable..................................................................................4-6

Data Cache and Write Buffer Operation .........................................................................................4-6

Data Cache Replacement Algorithm..............................................................................................4-8

Swap Instructions ........................................................................................................................4-8

Data Cache Organization .............................................................................................................4-9

Data Cache Lockdown .................................................................................................................4-9

Cache Coherence................................................................................................................................4-10

Cache Cleaning when Lockdown is in Use.............................................................................................4-12

Implementation Notes ..........................................................................................................................4-12

Physical Address TAG RAM ................................................................................................................4-12

Appendix 5- Clock Modes

Overview .............................................................................................................................................5-1

Fastbus Mode.....................................................................................................................................5-2

Synchronous Mode..............................................................................................................................5-2

Asynchronous Mode............................................................................................................................5-3

S3C2410A MICROPROCESSOR

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