S3C2410A Просмотр технического описания (PDF) - Samsung

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производитель

S3C2410A

200MHz & 266MHz 32-Bit RISC Microprocessor

Samsung 

Table of Contents (Continued)

Chapter 12 USB Host Controller

Overview .............................................................................................................................................12-1

USB Host Controller Special Registers ..........................................................................................12-2

Chapter 13 USB Device Controller

Overview .............................................................................................................................................13-1

Feature.......................................................................................................................................13-1

USB Device Controller Special Registers ...............................................................................................13-3

Function Address Register (Func_Addr_Reg).................................................................................13-5

Power Management Register (Pwr_Reg)........................................................................................13-6

Interrupt Register (Ep_Int_Reg/Usb_Int_Reg)..................................................................................13-7

Interrupt Enable Register (Ep_Int_En_Reg/Usb_Int_En_Reg) ...........................................................13-9

Frame Number Register (Fpame_Num1_Reg/Frame_Num2_Reg) ....................................................13-10

Index Register (Index_Reg)...........................................................................................................13-11

End Point0 Control Status Register (Ep0_Csr) ...............................................................................13-12

End Point In Control Status Register (In_Csr1_Reg/In_Csr2_Reg) ....................................................13-14

End Point Out Control Status Register (Out_Csr1_Reg/Out_Csr2_Reg)............................................13-16

End Point FIFO Register (Epn_Fifo_Reg).......................................................................................13-18

Max Packet Register (Maxp_Reg).................................................................................................13-19

End Point Out Write Count Register (Out_Fifo_Cnt1_Reg/Out_Fifo_Cnt2_Reg) .................................13-20

DMA Interface Control Register (Epn_Dma_Con) ............................................................................13-21

DMA Unit Counter Register (Epn_Dma_Unit)..................................................................................13-22

DMA FIFO Counter Register (Epn_Dma_FIFO)...............................................................................13-23

DMA Total Transfer Counter Register (Epn_Dma_Ttc_L, M, H).........................................................13-24

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S3C2410A MICROPROCESSOR

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