S3C1860 Просмотр технического описания (PDF) - Samsung

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производитель

S3C1860

4-bit single-chip CMOS microcontroller

Samsung 

S3C1840

FUCTIONAL DESCRIPTION

Program Memory (ROM)

The S3C1840's program memory consists of a 1024-byte ROM, organized in 16 pages. Each page is 64 bytes

long. (See Figure 1-10).

ROM addressing is supported by a 10-bit register made up of two sub-registers: a 4-bit Page Address register

(PA), and a 6-bit Program Counter (PC).

Pages 0 through 15 (FH) can each access 64 (3FH) bytes.

ROM addressing occurs as follows: The 10-bit register selects one of the ROM's 1024-bytes. A new address is

then loaded into the PC register during each instruction cycle.

Unless a transfer-of -control instruction such as JP,CALL, or RET is encountered, the PC is loaded with the next

sequential 6-bit address in the page, PC + 1. In this case, the next address of 3FH would be 00H.

Only the PAGE instruction can change the Page Buffer (PB) to a specified value.

When a JP or CALL instruction is executed, and if the Status Flag is set to "1", the contents of the PB are loaded

into the PA register. If the Status Flag is "0", however, the JP or CALL is executed like NOP instruction in an

instruction cycle and the Status Flag is set to "1". After that, program execution proceeds.

Page-In Addressing

All instructions, including, JP and CALL, can be executed by page. (See Figure 1-8). When the Status Flag is

"1", a JP or CALL causes a program to branch to its address (operand) in a page.

PA

4

PB

PC

PC address to be jumped ; if SF = 1

Figure 1-8. Page-In Addressing

Page-To-Page Addressing

When a PAGE instruction occurs, and if the Status Flag is "1", a JP or CALL instruction will cause a program to

branch to its address (operand) across the page (See Figure 1-9).

PA

4

PB

PC

PB #n ; PAGE #n

PC address to be jumped ; if SF = 1

PA PB

NOTE: If SF = 0 then PC PC + 1

Figure 1-9. Page-to-Page Addressing

1-8

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