S2R72V18F14 Просмотр технического описания (PDF) - Seiko Epson Corp

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S2R72V18F14

S2R72V27

Seiko Epson Corp 

4. Explanation of Functions

4.4 Power Management

This LSI includes a power management function featuring two power management states for each

port, SLEEP and ACTIVE, together with the CPU_Cut power management state common for the

chip. (See Fig. 4-3.)

All function blocks are active in the ACTIVE state, whereas only the bare minimum circuits

necessary for restarting from standby mode are active in SLEEP state. CPU_Cut mode minimizes

power consumption attributable to the CPU-I/F input buffer.

Port 0 ACTIVE

Port 1 ACTIVE

CPU

-I/F

OSC

FIFO

PLL60

SIE_0 MTM_0

SIE_1 MTM_1

Port 0 ACTIVE

Port 1 SLEEP

CPU

-I/F

OSC

FIFO

PLL60

SIE_0 MTM_0

SIE_1 MTM_1

Port 0 SLEEP

Port 1 ACTIVE

CPU

-I/F

OSC

FIFO

PLL60

SIE_0 MTM_0

SIE_1 MTM_1

Port 0 SLEEP

Port 1 SLEEP

CPU

-I/F*

OSC

FIFO

PLL60

SIE_0 MTM_0

SIE_1 MTM_1

Port 0 CPU_Cut

Port 1 CPU_Cut

CPU

-I/F**

OSC

FIFO

PLL60

SIE_0 MTM_0

SIE_1 MTM_1

Active

Inactive

* The CPU-I/F is only partially active in SLEEP state.

The asynchronous access register can be accessed.

** CPU-I/F operation is suspended in CPU_Cut to minimize

power consumption attributable to the I/O input buffer.

Fig. 4-3 Power management states

6

EPSON

S2R72V18 Data Sheet (Rev. 1.00)

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