RTH010 Просмотр технического описания (PDF) - Unspecified
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RTH010 Datasheet PDF : 11 Pages
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RTH010 DATA SHEET REV F
Electrical Specification (Continued)
PARAMETER
SYMBOL
CONDITIONS, NOTE
TEST LEVEL
TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH1
Aperture Delay
Aperture Jitter
ta
After V(CLK1) - V(CLK1B) Goes Neg.
4
∆t
Jitter Free 1-GHz 0.5-Vpp CLK1(B)4,5
3
Settling Time to 1 mV
ts
At Hold Capacitors. ttrack1,min
Observed
4
Differential Pedestal/VIN6
4
Diff. Droop Rate/VIN
Hold Noise7
4
Per Sqrt(Hold Time)
4
Minimum CLK1 Freq.
fclk1, min
50% Duty Cycle Clock
2
Maximum CLK1 Freq.
fclk1, max 50% Duty Cycle Clock
2
Maximum Hold Time8
thold1, max
3
HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH1
Acquisition Time to 1 mV9
tacq
At Hold Caps, FSR Step At Input
4
Max. Acq. Slew Rate9
dvdt,max
At Hold Caps, FSR Step At Input
4
Rise Time9
tr
20 – 80%
3
Minimum Track Time
ttrack1,min thold1,max Observed
2
Recovery Time
Required Accumulated Track Time
After thold1,max Violation
3
TRACK-TO-HOLD SWITCHING AND HOLD STATE, TH2
Aperture Delay
ta2
Settling Time to 1 mV10
ts2
Differential Pedestal/VIN11
After V(CLK2) - V(CLK2B) Goes Neg.
4
At DTH Output. ttrack2,min Observed
4
4
Diff. Droop Rate/VIN
Hold Noise7
4
Per Sqrt(Hold Time)
4
Minimum CLK2 Freq.
fclk2,min
50% Duty Cycle Clock
2
Maximum CLK2 Freq.
fclk2,max
50% Duty Cycle Clock
2
Maximum Hold Time8
thold2,max
3
HOLD-TO-TRACK SWITCHING AND TRACK STATE, TH2
Minimum Track Time after
TH1 in Hold Mode12
ttrack2,min
thold2,max Observed
2
Recovery Time
Required Accumulated Track Time
After thold2,max Violation
3
POWER SUPPLY REQUIREMENTS
Positive Supply Voltage
VCC
1
VCC Current
ICC
1
Negative Supply Voltage
VEE
1
VEE Current
IEE
1
Power Dissipation
1
Warm-up Time13
After Power-up
2
MIN
70
1000
5
1000
10
4.75
-5.45
2.2
TYP
+60
100
300
-2
-1
50
8
250
15
0.4
+60
300
±0.25
-0.12
25
15
0.5
5.0
130
-5.2
325
2.35
MAX
130
200
1250
12
50
4
100
1250
20
4
5.25
180
-4.95
400
2.5
10
UNITS
ps
fs
ps
%
%/ns
µV/√ns
MHz
MHz
ns
ps
V/ns
ps
ns
ns
ps
ps
%
%/ns
µV/√ns
MHz
MHz
ns
ns
ns
V
mA
V
mA
W
s
4 The clock source jitter and the aperture jitter combine in an rms manner to yield the total sampling jitter. See Definition of Terms.
5 Device aperture jitter increases as the V(CLK1) – V(CLK1B) slew rate at the zero crossing decreases. See Theory of Operation.
6 The differential pedestal error is proportional to the input signal. For TH1 it corresponds to a track-to-hold gain ~ -0.17 dB. This
gain loss may be observed at the DTH output if TH2 is in track mode during the TH1 track-to-hold transition.
7 The variance of the hold noise is proportional to the hold time, thold. For example, for TH1, a 4-ns hold time, thold1, gives about
100 µV accumulated hold noise. TH1 and TH2 hold noise, up to the output sampling instant, should be rms added to the hold
mode integrated noise of the DTH.
8 Maximum hold time is determined by droop of single-ended hold capacitor voltages. The resulting shift of internal operating
voltages is not directly observable at the DTH outputs but eventually causes device performance degradation.
9 TH1 tacq, dvdt,max, and tr also apply to the reconstructed DTH output if sub-sampling a fast-edge repetitive wave form.
10 Output is settled ta2 + ts2 after CLK2(B) downward transition.
11 The differential pedestal error is proportional to the input signal. For TH2 it corresponds to a track-to-hold gain ~ ±0.02 dB.
12 ttrack2,min > ts, since the buffered TH1 output onto the TH2 hold capacitors lags behind the TH1 hold capacitor signal.
13 The part functions immediately and reaches specification after warm-up time.
The product specifications contained in this data sheet are subject to change. Rockwell Scientific Company reserves the right to make changes to its product
specifications at any time without notice. The information furnished herein is believed to be accurate; however, no responsibility is assumed for its use.
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