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LH28F800SU

8M (512K × 16, 1M × 8) Flash Memory

Sharp Electronics 

LH28F800SU

8M (512K × 16, 1M × 8) Flash Memory

The LH28F800SU will be available in a 56-pin,

1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack-

age.This form factor and pinout allow for very high board

layout densities.

A Command User Interface (CUI) serves as the sys-

tem interface between the microprocessor or

microcontroller and the internal memory operation.

Internal Algorithm Automation allows Byte/Word

Writes and Block Erase operations to be executed

using a Two-Write command sequence to the CUI in

the same way as the LH28F008SA 8M Flash memory.

A Superset of commands have been added to the

basic LH28F008SA command-set to achieve higher

write performance and provide additional capabilities.

These new commands and features include:

• Page Buffer Writes to Flash

• Command Queuing Capability

• Automatic Data Writes During Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Writes in 8-bit Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte or

word increments typically within 8 µs, a 25% improve-

ment over the LH28F008SA. A Block Erase operation

erases one of the 16 blocks in typically 0.7 seconds,

independent of the other blocks, which is about 55%

improvement over the LH28F008SA.

The LH28F800SU incorporates two Page Buffers of

256 Bytes (128 Words) each to allow page data writes.

This feature can improve a system write performance

over previous flash memory devices.

All operations are started by a sequence of Write

commands to the device. Three Status Registers (de-

scribed in detail later) and a RY »/BY » output pin provide

information on the progress of the requested operation.

While the LH28F008SA requires an operation to com-

plete before the next operation can be requested, the

LH28F800SU allows queuing of the next operation while

the memory executes the current operation. This elimi-

nates system overhead when writing several bytes in a

row to the array or erasing several blocks at the same

time. The LH28F800SU can also perform write opera-

tions to one block of memory while performing erase of

another block.

The LH28F800SU provides user-selectable block

locking to protect code or data such as Device Drivers,

PCMCIA card information, ROM-Executable O/S or Ap-

plication Code. Each block has an associated non-

volatile lock-bit which determines the lock status of the

block. In addition, the LH28F800SU has a master Write

Protect pin (WP ») which prevents any modification to

memory blocks whose lock-bits are set.

The LH28F800SU contains three types of Status

Registers to accomplish various functions:

• A Compatible Status Register (CSR) which is

100% compatible with the LH28F008SA Flash

memory’s Status Register. This register, when used

alone, provides a straightforward upgrade capabil-

ity to the LH28F800SU from a LH28F008SA

based design.

• A Global Status Register (GSR) which informs the

system of command Queue status. Page Buffer sta-

tus, and overall Write State Machine (WSM) status.

• 16 Block Status Register (BSRs) which provide

block-specific status information such as the block

lock-bit status.

The GSR and BSR memory maps for Byte-Wide and

Word-Wide modes are shown in Figures 5 and 6.

The LH28F800SU incorporates an open drain

RY /» BY » output pin. This feature allows the user to OR-

tie many RY/» BY» pins together in a multiple memory con-

figuration such as a Resident Flash Array.

The LH28F800SU also incorporates a dual chip-en-

able function with two input pins. CE 0» and CE 1» . These

pins have exactly the same functionality as the regular

chip-enable pin CE » on the LH28F008SA. For minimum

chip designs, CE 1» may be tied to ground and use CE »0

as the chip enable input. The LH28F800SU uses the

logical combination of these two signals to enable or

disable the entire chip. Both CE »0 and CE 1» must be ac-

tive low to enable the device and if either one

becomes inactive, the chip will be disabled. This fea-

ture, along with the open drain RY /» BY » pin, allows the

system designer to reduce the number of control pins

used in a large array of 8M devices.

The BY T» E » pin allows either x8 or x16 read/writes to

the LH28F800SU. BYT» E » at logic low selects 8-bit mode

with address A0 selecting between low byte and high

byte. On the other hand, BY »TE » at logic high enables

16-bit operation with address A1 becoming the lowest

order address and address A0 is not used (don’t care).

A block diagram is shown in Figure 3.

The LH28F800SU is specified for a maximum

access time of each version, as follows:

OPERATING

TEMPERATURE

0 - 70°C

0 - 70°C

0 - 70°C

0 - 70°C

VCC SUPPLY

4.75 - 5.25 V

4.5 - 5.5 V

3.0 - 3.6 V

2.7 - 3.6 V

MAX. ACCESS

(TACC)

70 ns

80 ns

120 ns

160 ns

6

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