RT8113 Просмотр технического описания (PDF) - Richtek Technology

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RT8113

Single Phase VR11.1 PWM Controller with 7-bit VID

Richtek Technology 

RT8113

tD1 is the delay time from power on reset state to the beginning of VOUT rising.

tD1 = 1600μs +

0.7V x CSS

16μA

tD2 is the soft-start time from VOUT = 0 to VOUT = VBOOT.

t D2

=

VBOOT x CSS

16μA

tD3 is the dwelling time for VOUT = VBOOT.

tD3 ≅ 800μs.

tD4 is the soft-start time from VOUT = VBOOT to VOUT = VDAC.

tD4 ≅

VDAC - VBOOT x Css

16μA

tD5 is the power good delay time.

tD5 ≅ 1600μs.

Dynamic VID

The RT8113 can accept VID input changing while the

controller is running. This allows the output voltage (VOUT)

to change while the DC/DC converter is running and

supplying current to the load. This is commonly referred

to as VID on-the-fly (OTF). A VID OTF can occur under

either light or heavy load conditions. The CPU changes

the VID inputs in multiple steps from the start code to the

finish code. This change can be positive or negative.

Theoretically, VOUT should follow VDAC, which is a

staircase waveform, but in real application, the bandwidth

of the converter is finite while the staircase waveform needs

infinite bandwidth to follow. Thus, undesired VOUT overshoot

(when VDAC changes up) or undershoot (when VDAC

changes down) is often observed in these type of designs.

However, for the RT8113, as mentioned before in the

Soft-Start section, VDAC slew rate is limited by ISS2/CSS

when PGOOD = high. This slew rate limiter works as a

low-pass filter of VDAC and makes the bandwidth of VDAC

waveform finite. By smoothening VDAC staircase waveform,

VOUT will no longer overshoot or undershoot. On the other

hand, CSS will increase the settling time of VOUT during

VID OTF. In most cases, a 1nF to 30nF ceramic capacitor

will be suitable for CSS.

Output Voltage Differential Sensing

The RT8113 uses a high-gain low-offset error amplifier for

differential sensing. The CPU voltage is sensed between

the FB and FBRTN pins. A resistor (RFB) connects the FB

pin with the positive remote sense pin of the CPU (VCCP),

while the FBRTN pin connects directly to the negative

remote sense pin of the CPU (VCCN). The error amplifier

compares VEAP (= VDAC − VADJ) with the VFB to regulate

the output voltage.

No-Load Offset

In Figure 5, IOFSN and IOFSP are used to generate no-load

offset. Either IOFSN or IOFSP is active during normal

operation. Connect a resistor from OFS pin to GND to

activate IOFSN. IOFSN flows through RFB from the FB pin to

VCCP. In this case, a negative no-load offset voltage (VOFSN)

is generated.

VOFSN

= IOFSN

x RFB

=

0.8 x RFB

ROFS

Connect a resistor from the OFS pin to VCC5 to activate

IOFSP. IOFSP flows through RFB from the VCCP to the FB

pin. In this case, a positive no-load offset voltage (VOFSP)

is generated.

VOFSP

= IOFSP

x RFB

=

6.4 x RFB

ROFS

www.richtek.com

14

DS8113-02 April 2011

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