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RT8113 Просмотр технического описания (PDF) - Richtek Technology

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RT8113 Datasheet PDF : 21 Pages
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RT8113
After VOUT ramps to VBOOT, the RT8113 stays in this state
for 800μs (tD3) waiting for valid VID code sent by CPU.
After receiving valid VID code, VOUT continues ramping up
or down to the voltage specified by VID code. After VOUT
ramps to VEAP = VDAC VADJ, the RT8113 stays in this
state for 1600μs (tD5) and then asserts PGOOD = high.
The ramping slew rate of tD2 and tD4 is controlled by the
external capacitor connected to SS pin. The voltage of
the SS pin will always be VEAP+0.7V, where the mentioned
0.7V is the typical turn-on threshold of an internal power
switch. Before PGOOD = high, the slew rate of VEAP is
limited to 16μA/CSS. When PGOOD = high, the slew rate
of VEAP is limited to 160μA/CSS, which is 10 times faster
than soft start slew rate for dynamic VID feature. The soft
start waveform is shown in Figure 4.
C2
C3 R3 C1 R2
R1
VOUT
Soft Start Current (ISS)
is Limited and Variant
VDAC
Soft Start
Circuit
FB
COMP
-
EA
+
EAP
(Error AMP Positive Input)
ISS
SS
ADJ
CSS
RADJ
Figure 3. Circuit for Soft-Start and Dynamic VID
VCC5
VCC12
VDAC
4.6V
9.6V
PGOOD
tD1
tD2
tD3
tD4
tD5
Figure 4. Soft-Start Wave forms
SS
VOUT
VBOOT
DS8113-02 April 2011
www.richtek.com
13

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