RT8068A Просмотр технического описания (PDF) - Richtek Technology
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RT8068A Datasheet PDF : 13 Pages
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RT8068A
The input capacitor is used to supply the input RMS
current, which can be approximately calculated using the
following equation :
IIN_RMS = ILOAD ×
VOUT
VIN
× ⎛⎜⎝1−
VOUT
VIN
⎞⎟⎠
The next step is selecting a proper capacitor for RMS
current rating. One good design is using more than one
capacitor with low equivalent series resistance (ESR) in
parallel to form a capacitor bank.
The input capacitance value determines the input ripple
voltage of the regulator. The input voltage ripple can be
approximately calculated using the following equation :
ΔVIN
=
IOUT(MAX) × 0.25
CIN × fSW
For example, if IOUT_MAX = 3A, CIN = 20μF, fSW = 1MHz,
the input voltage ripple will be 37.5mV.
Output Capacitor Selection
The output capacitor and the inductor form a low pass
filter in the buck topology. In steady state condition, the
ripple current flowing into/out of the capacitor results in
ripple voltage. The output voltage ripple (VP-P) can be
calculated by the following equation :
VP_P
= LIR ×ILOAD(MAX) × ⎛⎜⎝ESR +
1
8 × COUT × fSW
⎞⎟⎠
When load transient occurs, the output capacitor supplies
the load current before the controller can respond.
Therefore, the ESR will dominate the output voltage sag
during load transient. The output voltage undershoot (VSAG)
can be calculated by the following equation :
VSAG = ΔILOAD ×ESR
For a given output voltage sag specification, the ESR value
can be determined.
Another parameter that has influence on the output voltage
sag is the equivalent series inductance (ESL). The rapid
change in load current results in di/dt during transient.
Therefore, the ESL contributes to part of the voltage sag.
Using a capacitor with low ESL can obtain better transient
performance. Generally, using several capacitors
connected in parallel can have better transient performance
than using a single capacitor for the same total ESR.
Unlike the electrolytic capacitor, the ceramic capacitor has
relatively low ESR and can reduce the voltage deviation
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during load transient. However, the ceramic capacitor can
only provide low capacitance value. Therefore, use a mixed
combination of electrolytic capacitor and ceramic capacitor
to obtain better transient performance.
Power Good Output (PGOOD)
PGOOD is an open-drain type output and requires a pull-
up resistor. PGOOD is actively held low in soft-start,
standby, and shutdown. It is released when the output
voltage rises above 90% of nominal regulation point. The
PGOOD signal goes low if the output is turned off or is
10% below its nominal regulation point.
Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
voltage. When under voltage protection is enabled, both
UGATE and LGATE gate drivers will be forced low if the
output is less than 66% of its set voltage threshold. The
UVP will be ignored for at least 3ms (typ.) after start up or
a rising edge on the EN threshold. Toggle EN threshold or
cycle VIN to reset the UVP fault latch and restart the
controller.
Over Voltage Protection (OVP)
The RT8068A is latched once OVP is triggered and can
only be released by toggling EN threshold or cycling VIN.
There is a 10μs delay built into the over voltage protection
circuit to prevent false transition.
Over Current Protection (OCP)
The RT8068A provides over current protection by detecting
high side MOSFET peak inductor current. If the sensed
peak inductor current is over the current limit threshold
(4A typ.), the OCP will be triggered. When OCP is tripped,
the RT8068A will keep the over current threshold level
until the over current condition is removed.
Thermal Shutdown (OTP)
The device implements an internal thermal shutdown
function when the junction temperature exceeds 150°C.
The thermal shutdown forces the device to stop switching
when the junction temperature exceeds the thermal
shutdown threshold. Once the die temperature decreases
below the hysteresis of 20°C, the device reinstates the
power up sequence.
DS8068A-03 May 2011
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