M66255FP Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M66255FP

8192 × 10-BIT LINE MEMORY (FIFO)

MITSUBISHI ELECTRIC  

MITSUBISHI 〈DIGITAL ASSP〉

M66255FP

8192 × 10-BIT LINE MEMORY (FIFO)

• Shortest read of data “n” written in cycle n

Cycle n–1 on read side should be started after end of cycle n+1 on write side

When the start of cycle n–1 on read side is earlier than the end of cycle n+1 on write side, output Qn of cycle n becomes invalid.

In the figure shown below, the read of cycle n–1 is invalid.

WCK

Dn

RCK

Qn

Cycle n

Cycle n+1

Cycle n+2

Cycle n+3

(n)

(n+1)

Cycle n–2

(n+2)

Cycle n–1

(n+3)

Cycle n

invalid

(n)

• Longest read of data “n” written in cycle n: 1-line delay

Cycle n <1>* on read side should be started when cycle n <2>* on write is started

Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1>* and the start of writing side n cycle <2>* over-

lap each other.

WCK

Cycle n <1>*

Cycle 0 <2>*

Cycle n <2>*

Dn

(n–1)<1>*

(n)<1>*

RCK

Cycle n <0>*

Qn

(n–1)<0>*

(n)<0>*

(0) <2>*

Cycle 0 <1>*

(n–1)<2>*

(n)<2>*

Cycle n <1>*

(0)<1>*

(n–1)<1>*

(n)<1>*

<0>*, <1>* and <2>* indicates a line value.

10

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