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RF2968 Просмотр технического описания (PDF) - RF Micro Devices

Номер в каталоге
Компоненты Описание
производитель
RF2968
RFMD
RF Micro Devices RFMD
RF2968 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
RF2968
Preliminary
11
Register 6 - IF Register 4 (Write-Only)
Bit Number
Bit Name
0-15
N/A
Not Assigned
Comments
Register 7 - PLL Control (Write-Only)
Bit Number
Bit Name
Comments
15
Set_Tx_PLL_LF_Ext Configures the LPO pin as a test pin when bits LPO[1:0] are set high.
1: Test mode. LPO is connected to the IF PLL loop filter of the transmitter.
(See “Special Modes: Transmitter Test Mode”.)
0: Normal mode. LPO is not connected to the IF PLL loop filter of the trans-
mitter.
13 - 14
PLLDel [1:0]
Determines the time in which the PLL remains in high bandwidth mode
before switching to low bandwidth mode. In high bandwidth mode, the PLL
loop bandwidth is optimized for fast frequency locking. In low bandwidth
mode, the loop bandwidth is optimized for low phase noise. See below. See
also pin descriptions of D0 and RSHUNT, and bit PLL_BW (Register 5, Bit
1).
12
RSSI_Test
Configures the RSSI circuitry to operate continuously for test purposes.
1: Test mode. Continuous operation.
0: Normal mode. Packet-based operation.
9 - 11
DivR [2:0]
Selects the external crystal frequency. See below.
8
TX_EN
Powers up the TX voltage and current bias circuits and the TX PLL’s ICO
voltage threshold set circuit.
7
RX_EN
Powers up the RX voltage and current bias circuits.
0-6
PLL [6:0]
Sets the RF PLL frequency. See below.
PLLDel [1:0]:
PLLDel [1:0]
00
01
10
11
Delay (us)
0
50
100
150
DivR [2:0]:
DivR [2:0]
011
100
101
110
111
Crystal Freq (MHz)
12
10
11
13
20
11-132
Rev A13 010912

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