DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

RF2968 Просмотр технического описания (PDF) - RF Micro Devices

Номер в каталоге
Компоненты Описание
производитель
RF2968
RFMD
RF Micro Devices RFMD
RF2968 Datasheet PDF : 20 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
RF2968
Preliminary
Application Information
Baseband Interface
The RF2968 RF transceiver serves as the physical layer (PHY) in a Bluetooth system and supports the BlueRF interface
between PHY and baseband devices. The RF2968 contains the data demodulation, DC compensation, and data and
clock extraction circuitry while the access code correlator function takes place in the baseband.
There are two interfaces between the RF2968 and the baseband. The serial interface provides the path for control data
exchange, and the bidirectional interface provides the path for modem, timing, and chip power control signals. Figure 1
shows bidirectional signals with arrowheads on both ends of the line.
BDATA1
BPKTCTL
BXTLEN
BRCLK
BnPWR
BDDATA
BDCLK
BnDEN
Figure1. Baseband/RF2968 Interface
11
Serial Interface
Control data is exchanged between the RF2968 and the baseband by means of the DBus serial interface protocol.
BDCLK, BDDATA, and BnDEN are the signals comprising the serial interface. The baseband is the master device, initi-
ating all accesses to the RF2968 registers. The data registers of the RF2968 are programmed or recalled according to
the specified command format and address assignments. Data packets are transmitted MSB first.
Serial Data Packet Format
Field
Device Address
Read/Write
Register Address
Data
Number of Bits
3 [A7:A5]
1 [R/W]
5 [A4:A0]
16 [D15:D0]
Comments
“101” for PHY
“1”=Read, “0”=Write
Maximum of 32 registers
The RF2968 is programmed in Write mode and returns its register contents
in Read mode.
During a write, the baseband drives out each bit of the packet on the falling edge of BDCLK. The RF2968’s data register
is updated with the shift register contents on the first falling edge of BDCLK after BnDEN is driven high. See Figure 2.
BDCLK
BDDATA
BnDEN
A7
A6 A5
...
A4
A3
A2
A1
... A0 D15 D14
D2
D1
D0
don't
care
A7
A6
R/W= write = 0
Figure 2. DBus Write Programming Diagram
11-128
Rev A13 010912

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]