ADSP-21MOD980N-000 Просмотр технического описания (PDF) - Analog Devices

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ADSP-21MOD980N-000

MultiPort Internet Gateway Processor

Analog Devices 

PRELIMINARY TECHNICAL DATA

ADSP-21mod980N For current information contact Analog Devices at (800) ANALOGD

A clock output (CLKOUT) signal is generated by the pro-

cessor at the processor’s cycle rate. This can be enabled and

disabled by the CLKODIS bit in the SPORT0 Autobuffer

Control Register.

RESET

The RESET signals initiate a reset of each modem proces-

sor in the ADSP-21mod980N. The RESET signals must be

asserted during the power-up sequence to assure proper ini-

tialization. RESET during initial power-up must be held

long enough to let the internal clocks stabilize. If RESETs

are activated any time after power up, the clocks continue to

run and do not require stabilization time.

The power-up sequence is defined as the total time required

for the oscillator circuits to stabilize after a valid VDD is

applied to the processors, and for the internal phase-locked

loops (PLL) to lock onto the specific frequency. A mini-

mum of 2000 CLKIN cycles ensures that the PLLs have

locked, but this does not include the oscillators’ start-up

time. During this power-up sequence, the RESET signals

should be held low. On any subsequent resets, the RESET

signals must meet the minimum pulse width specification,

tRSP.

The RESET input contains some hysteresis; however, if you

use an RC circuit to generate your RESET signals, the use

of an external Schmidt triggers are recommended.

The RESET for each individual modem processor sets the

internal stack pointers to the empty stack condition, masks

all interrupts and clears the MSTAT register. When a

RESET is released, if there is no pending bus request and

the modem processor is configured for booting, the

boot-loading sequence is performed. The first instruction is

fetched from on-chip program memory location 0x0000

once boot loading completes.

MEMORY ARCHITECTURE

The ADSP-21mod980N provides a variety of memory and

peripheral interface options for Modem Processor 1. The

key functional groups are Program Memory, Data Memory,

Byte Memory, and I/O. Refer to the following figures and

tables for PM and DM memory allocations in the

ADSP-21mod980N.

The ADSP-21mod980N modem pool operates in one

memory mode: Slave Mode. The following figures and

tables describe the memory of the ADSP-21mod980N:

• Figure on page 10 shows Program Memory

• Table on page 10 shows the generation of address bits

based on the PMOVLAY values

• Figure on page 11 shows Data Memory

• Table on page 11 shows the generation of address bits

based on the DMOVLAY values. Access to external

memory is not available

PM MODE B = 0

ALWAYS

ACCESS IBLE

AT ADDRESS

0x0000 - 0x1FFF

ACCESSIBLE WHEN

PM OVLAY = 0

0x2000 -

0x3FFF

0x2000 -

0x3FFF

ACCESSIBLE WHEN

PM OVLAY = 4

ACCESSIBLE WHEN

PM OVLAY = 5

IN T ER N A L

MEMORY

ACCESSIBLE

WHEN

PM OVLAY = 6

AC CESS IBLE

WHEN

PM OVLAY = 7

0x2000 -

0x3FFF

0x2000 -

0x3FFF

0x2000 -

0x3FFF

PROGRAM MEMORY

MODE B=0 ADDRESS

0x3FFF

8K INTERNAL

PMOVLAY =

0, 4, 5, 6, 7

8K

INTERNAL

0x2000

0x1FFF

0x0000

Figure 4. Program Memory Map

Table 4. PMOVLAY bits

PMOVLAY Memory A13

A[12:0]

0, 4, 5, 6, 7 Internal Not

Not Applicable

Applicable

10

6/2001 REV. PrB

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