MTV012A Просмотр технического описания (PDF) - Myson Century Inc
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MTV012A Datasheet PDF : 14 Pages
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MYSON
TECHNOLOGY
MTV012A
P2.1
P2.2
P2.3
DA13/P2.4
DA12/P2.5
DA11/P2.6
DA10/P2.7
STOUT/P4.2
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
VDD
I/O
22 General purpose I/O.
I/O
23 General purpose I/O.
I/O
24 General purpose I/O.
I/O
25 PWM DAC output / General purpose I/O (open-drain).
I/O
26 PWM DAC output / General purpose I/O (open-drain).
I/O
27 PWM DAC output / General purpose I/O (open-drain).
I/O
28 PWM DAC output / General purpose I/O (open-drain).
O
29 Self-test video output / General purpose output.
O
30 PWM DAC output (open-drain).
O
31 PWM DAC output (open-drain).
O
32 PWM DAC output (open-drain).
O
33 PWM DAC output (open-drain).
O
34 PWM DAC output (open-drain).
O
35 PWM DAC output (open-drain).
O
36 PWM DAC output (open-drain).
O
37 PWM DAC output (open-drain).
O
38 PWM DAC output (open-drain).
O
39 PWM DAC output (open-drain).
-
40 Positive power supply.
3.0 FUNCTIONAL DESCRIPTION
1. 8051 CPU Core
MTV012A includes all the 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within
MTV012A.
1.2 Port0, port3.3 and ports3.5 ~ 3.7 are not general purpose I/O ports. They are dedicated to monitoring
control/DAC pins.
1.3 INT1 and T1 input pins are not provided.
1.4 Ports2.4 ~ 2.7 are shared with DAC pins; ports3.0 ~ 3.2 and port3.4 are shared with monitor control
pins.
In addition, there are 2 timers, 5 interrupt sources and a serial interface compatible with the standard
8051. The Txd/Rxd (P3.0/P3.1) pins are shared with the DDC interface. INT0/T0 pins are shared with
the IIC interface. An extra option can be used to switch the INT0 source from P3.2 to P2.0. This feature
maintains an external interrupt source when the IIC interface is enabled.
Note: All registers listed in this document reside in the external RAM area (XFR). For the internal
RAM memory map, please refer to the 8051 spec.
reg name addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
PADMOD 30h (w) SINT0
X
DDCE
IICE
DA13E DA12E DA11E DA10E
SINT0 = 1
=0
DDCE = 1
=0
IICE = 1
=0
DA13E = 1
=0
DA12E = 1
=0
→ INT0 source is pin #21.
→ INT0 source is pin #12.
→ Pin #10 is HSCL; pin #11 is HSDA.
→ Pin #10 is P3.0/Rxd; pin #11 is P3.1/Txd.
→ Pin #12 is ISDA; pin #14 is ISCL.
→ Pin #12 is P3.2/(INT0*); pin #14 is P3.4/T0.
→ Pin #25 is DA13.
→ Pin #25 is P2.4.
→ Pin #26 is DA12.
→ Pin #26 is P2.5.
MTV012A Revision 1.1 12/23/1998
3/14
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