INT100S Просмотр технического описания (PDF) - Power Integrations, Inc

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INT100S

Low-Side and High-side Drive with Simultaneous Conduction Lockout

Power Integrations, Inc 

Pin Functional Description

Pin 1:

V supplies power to the logic, high-

DD

side interface, and low-side driver.

Pin 2:

Active-low logic level input HS IN

controls the high-side driver output.

Pin 3:

Active-high logic level input LS IN

controls the low-side driver output.

Pin 4, 5:

COM connection is used as the analog

reference point for the circuit.

Pin 7:

LS RTN is the power reference point for

the low-side circuitry, and should be

connected to the source of the low-side

MOSFET and to the COM pin.

Pin 8:

LS OUT is the driver output which

controls the low-side MOSFET.

Pin 11:

HS OUT is the driver output which

controls the high-side MOSFET.

INT100

Pin 12,13,14:

HS RTN is the power reference point

for the high-side circuitry, and should be

connected to the source of the high-side

MOSFET.

Pin 15:

V supplies power to the high-side

DDH

control logic and output driver. This is

normally connected to a high-side

referenced bootstrap circuit or can be

supplied from a separate floating power

supply.

INT100 Functional Description

5 V Regulators

Both low-side and high-side driver

circuits incorporate a 5 V linear regulator

circuit. The low-side regulator provides

the supply voltage for the control logic

and high-voltage level shift circuit. This

allows HS IN and LS IN to be directly

compatible with 5 V CMOS logic

without the need of an external 5 V

supply. The high-side regulator provides

the supply voltage for the noise rejection

circuitry and high-side control logic.

Undervoltage Lockout

The undervoltage lockout circuit for the

low-side driver disables both the LS

OUT and HS OUT pins whenever the

VDD power supply falls below typically

9.0 V, and maintains this condition until

the VDD power supply rises above

typically 9.35 V. This guarantees that

both MOSFETs will remain off during

power-up or fault conditions.

The undervoltage lockout circuit for the

high-side driver disables the HS OUT

pin whenever the VDDH power supply

falls below typically 9.0 V, and maintains

this condition until the VDDH power

supply rises above typically 9.35 V.

This guarantees that the high-side

MOSFET will be off during power-up

or fault conditions.

Level Shift

The level shift control circuitry of the

low-side driver is connected to integrated

high-voltage N-channel MOSFET

transistors which perform the level-

shifting function for communication to

the high-side driver. Controlled current

capability allows the drain voltage to

float with the high-side driver. Two

individual channels produce a true

differential communication channel for

accurately controlling the high-side

driver in the presence of fast moving

high-voltage waveforms. The high

voltage level shift transistors employed

exhibit very low output capacitance,

minimizing the displacement currents

between the low-side and high-side

drivers during fast moving voltage

transients created during switching of

the external MOSFETs. As a result,

power dissipation is minimized and noise

immunity optimized.

The pulse circuit provides the two high-

voltage level shifters with precise timing

signals. These signals are used by the

discriminator to reject spurious noise.

The combination of differential

communication with the precise timing

provides maximum immunity to noise.

Simultaneous Conduction Lockout

A latch prevents the low-side driver and

high-side driver from being on at the

same time, regardless of the input signals.

Delay Circuit

The delay circuit matches the low-side

propagation delay with the combination

of the pulse circuit, high voltage level

shift, and high-side driver propagation

delays. This ensures that the low-side

driver and high-side driver will never be

on at the same time during switching

transitions in either direction.

Driver

The CMOS drive circuitry on both low-

side and high-side driver ICs provide

drive power to the gates of the external

MOSFETs. The drivers consist of a

CMOS buffer capable of driving external

transistor gates at up to 15 V.

3 C

6/96

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