WAVEFORMS (Continued)
CLK NPRD NPWR TIMING (CKM e 1)
M80287
CLK RESET TIMING (CKM e 0)
271029 – 20
NOTE
Reset must meet timing shown to guarantee known phase of internal d3 circuit
CLK NPRD NPWR TIMING (CKM e 0)
271029 – 21
271029 – 22
NOTE
Reset NPWR NPRD are inputs asynchronous to CLK Timing requirements for RESET NPWR and NPRD are given for
testing purposes only to assure recognition at a specific CLK edge
9