PM73122 Просмотр технического описания (PDF) - PMC-Sierra

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PM73122

ATM ADAPTATION LAYER 1 SEGMENTATION AND REASSEMBLY PROCESSOR-32

PMC-Sierra 

RELEASED

DATASHEET

PMC-1981419

ISSUE 7

PM73122 AAL1GATOR-32

32 LINK CES/DBCES AAL1 SAR PROCESSOR

Issue Issue Date

No.

7

June 2001

Details of Change

Changed DC_INT_EN to SYNC_INT_EN in operations section.

In DC Characteristics, corrected IDDOP(2.7) for HS mode.

In Operations section, clarified function of SBI Parity Error Detection and recommended setting

the BUSMASTER bit in the PHY SBI device.

Added note at beginning of AC Characteristics recommending that transition times on clock inputs

is less than 15 ns.

Corrected Ram Interface Timing

In Memory Mapped Register Section added CSD_BYTES_LEFT register definition in

T_QUEUE_TABLE. Added hidden bits in QUE_CREDITS word and added

R_DBCES_BM_IN_NEXT to R_TOT_LEFT memory register and changed

R_DBCES_BM_IN_NEXT bit to R_DBCES_BM_INACT in R_STATE_0 memory register.

Clarified C1FP signal definition in SBI Signal Definition section.

Changed “Out of Band” idle detection mode to “Processor Controlled” idle detection mode in Idle

Detection section of Functional Description.

Updated PCR section in Functional Description

Added SRTS patent legal note to footer of last page

Corrected T1/E1 Link Rate Table (reversed polarity of C1FP)

Corrected cross reference in ADD QUEUE FIFO section

Removed equations from partial cell PCR section and replaced with summary table.

Added reference by RL_CLK that clock can not be gapped and must have jitter less than .3 UI if

using SRTS.

Added minor clarifications, including: R_LINE_STATE location not used in UDF-HS mode,

explanation of PCR for UDF-ML, removed references to E3 over SBI, added recommendation to

tie unused TL_CLK pins high in UDF-HS modes, renamed RPHY_ADD_RSX pin to

RPHY_ADD[4]/RSX to match Tx side, removed ‘sampled on rising edge’ from ADETECT pin

description, added that PAGE bit is a don’t care when accessing SBI Control RAM’s, clarified max

RSTB timing and max 400 SYSCLK rd/wr timing, clarified T1/E1 granularity in SBI mode(at

DA1SP level), E1_w_T1_sig mode not supported over SBI, clarified that SN state machines

freeze during underruns.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

iii

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