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PM73122

ATM ADAPTATION LAYER 1 SEGMENTATION AND REASSEMBLY PROCESSOR-32

PMC-Sierra 

RELEASED

DATASHEET

PMC-1981419

ISSUE 7

PM73122 AAL1GATOR-32

32 LINK CES/DBCES AAL1 SAR PROCESSOR

Issue Issue Date Details of Change

No.

6

May 2001

Added section: Changes from Rev B to Rev C.

Added “BUSMASTER” bit in SBI_BUS_CFG_REG, along with description.

Clarified NODROP_IN_START and DROPPED_CELL counter functionality is that

NODROP_IN_START has no effect for ROBUST SN Processing and UDF-HS mode.

In LIN_STR_MODE added cross reference to HS Operations section for Dual DS3 mode.

Corrected “Out of Band Signaling Idle Detection” section with respect to RX and TX CAS.

Fixed Robust SN processing Figure.

Added note in SN PROCESSING register to clarify that only ROBUST_SN_EN or DISABLE_SN

can be set, not both.

Only SBI mapping ram has 2 pages not SBI control RAM.

Sometimes An_SW_RESET needs to be used with high speed queue. Updated Operations

section and An_SW_RESET description.

Added times when OFFSET needs to be set to FRAMES_PER_CELL in OFFSET bit description.

Clarified MVIP-90 configuration in the Operations section

Changed DC_INT from link to tributary.

Flipped HIZDATA and HIZIO.

In DC Characteristics, made operating current for I/O typical, added .5 ns margin to C1FP hold

and SBI Tz. Also applied C1FP timing to C1FP_ADD also.

Default value corrected for MIN_DEPTH for DS3 Register.

Clarified and/or corrected “INSBI/EXSBI Programming Steps” section, “SBI Operation” section,

tributary mapping sequences in “Programming Sequence for SBI” section and lack of depth check

support in SBI Synchronous Mode.

Added statements describing that UDF_HS Loopback Mode requires that the High Speed Queue

be reset, that SPE Activation Must Occur After Tributaries are Enabled, that SPE Activation must

occur after tributaries are enabled.

Updated applications section with new PMC devices: PM8316 TEMUX-84, PM7341 S/UNI-IMA-

84.

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

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