PLL103-53XC Просмотр технического описания (PDF) - PhaseLink Corporation

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PLL103-53XC

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

PhaseLink Corporation 

Preliminary PLL103-53

DDR SDRAM Buffer with 5 DDR or 3 SDR/3 DDR DIMMS

2. BYTE 7: Outputs Register (1=Enable, 0=Disable)

Bit

Pin#

Default Description

Bit 7

38, 37

1

DDR7T, DDR7C

Bit 6

36, 35

1

DDR6T, DDR6C

Bit 5

21, 22

1

DDR5T_SDRAM8, DDR5C_SDRAM9

Bit 4

19, 20

Bit 3

15, 16

1

DDR4T_SDRAM6, DDR4C_SDRAM7

1

DDR3T_SDRAM4, DDR3C_SDRAM5

Bit 2

10, 11

1

DDR2T_SDRAM2, DDR2C_SDRAM3

Bit 1

6, 7

1

DDR1T_SDRAM0, DDR1C_SDRAM1

Bit 0

4, 5

1

DDR0T_SDRAM10, DDR0C_SDRAM11

47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991

Rev 12/01/00 Page 4

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