PLL102-109XM Просмотр технического описания (PDF) - PhaseLink Corporation
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PLL102-109XM Datasheet PDF : 10 Pages
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Preliminary PLL102-109
Programmable DDR Zero Delay Clock Driver
PIN DESCRIPTIONS
Name
VDD
GND
AVDD
AGND
CLKT(0:5)
CLKC(0:5)
CLK_INT
ADDR_SEL
N/C
FB_OUTT
FB_INT
SDATA
SCLK
Number
3,12,23
6,15,28
10
11
2,4,13,17,24,26
1,5,14,16,25,27
8
18
9,21
19
20
22
7
Type
Description
PWR
PWR
PWR
PWR
OUT
OUT
IN
IN
-
OUT
IN
I/O
IN
2.5V power supply.
Ground
Analog power supply (2.5V).
Analog ground.
“True” clocks of differential pair outputs.
“Complementary” clocks of differential pair outputs.
Single-ended 3.3V tolerant input.
If ADDR_SEL=0(default) Write condition (0xD4) or a read condition (0xD5)
If ADDR_SEL=1, Write condition (0xD6) or a read condition (0xD7)
Not connected.
“True” feedback output. Dedicated for external feedback. It switches at the
same frequency as the CLK_INT.
“True” feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
Serial data input for serial interface port.
Functionality
AVDD
2.5V (Nom)
2.5V (Nom)
GND
GND
INPUTS
CLK_INT
L
H
L
H
CLK_INC
H
L
H
L
CLKT
L
H
L
H
OUTPUTS
CLKC
H
L
H
L
FB_OUTT
L
H
L
H
PLL State
On
On
Bypass/Off
Bypass/Off
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Rev 02/26/03 Page 2
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